Sony SPP-A941 - Cordless Telephone With Answering System, Руководство по обслуживанию

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• IC Block Diagrams
U1 U2765B-AFSG3 (BASE RF Board)
U1 U2765B-AFSG3 (HAND RF Board)
U3 TB31202BFN-EL (HAND RF Board)
U10 TB31202BFN-EL (BASE RF Board)
U3 CAT93C46KI (BASE MAIN Board)
VCC/2
COMPARATOR
SLICER
LOCAL OSC
BUFFER
VCC2 LO REF LO IN GND2 NC VCC3 LIM1 OUT GND3 LIM2 IN LIM2 REF GND4 DEM NT
ANK
DEM T
ANK
DEM OUT
NC
A1 REF
A1 IN
GND1
MIX OUT
VCC1
MIX NOUT
LIM1 REF
LIM1 IN
RSSI
DA
TA
OUT
COM NIN
COM IN
SL IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A1
MIX
LIMITER
AMP
LIMITER
AMP
DE-
MODULATOR
RSSI
+
–
+
–
2 3 5 4 6 7
8
9 10
1
11 12
13
14 15 16
BUF
BUF
PROGRAMABLE
DIVIDER
PHASE
COMPARATOR
OUTPUT
SWITCH
L. OSC
REFERENCE
DIVIDER
LOCK
DET
CONTROL
CIRCUIT
1/2
1/2
1/2
BUF
1
––––––––
32, 33
1
––––––––
32, 33
PHASE
COMPARATOR
OUTPUT
PROGRAMABLE
DIVIDER
FIN1
VCC CP1
GND
LD CK
D
ATA
STB
FIN2 VCC CP2 GND SW XIN XOUT BO
U4 TA31103F (BASE MAIN Board)
U7 TA31103F (HAND MAIN Board)
U10 MC74HC595AF (BASE MAIN Board) U11 LP2953IM (HAND MAIN Board)
2 1
E-RECT PRE OUT PRE NF VCC VREF THROUG RO2 RIN EXP OUT RO1 COMP MUTE EXP MUTE
4
FIL1 OUT
3
FIL2 IN
FIL2 OUT
+
–
+
–
5 9 8 7
6
IN2
C-RECT
C-NF
FIL1 IN
COMP OUT
10 11 12
24 20 21 22 23 19 17
18
15 14 13 16
GND
MIC IN
MIC OUT
MIC NF
∆
G
VREF
+
–
VREF
VREF
SWITCH
CONTROL
+
– +
–
MIC AMP
SUM
AMP
+
–
+
–
∆
G
VREF
VREF PRE AMP
SUM
AMP
RO1
AMP
COMP
MUTE
EXP
MUTE
THROUG
THROUGH
IN 2
AMP
FILTER
AMP 1
FILTER
AMP 2
+
–
VREF
RO2
AMP
+
–
1
2 3 4 5 6 7 8
9 10 16 15 14 13 12 11
SHIFT REGISTER
LATCH
PARALLEL DATA
OUTPUT
GND
VCC
LATCH CLOCK PARALLEL DATA OUTPUT SERIAL DATA INPUT OUTPUT ENABLE SHIFT CLOCK SERIAL DATA OUTPUT RESET
QB
QC QD QE QF QG QH
SQH
A
QA
2
3
1
8
9
10
11
12
13
14
15
7
5
6
4
SHUT DOWN
ERROR
NC
GND
NC
OUTPUT
SENSE
GND
VREF
COMP IN
COMP OUT
GND
INPUT
FEEDBACK
5V TAP
+
–
+
–
+
–
+
–
ERROR
AMP
SHUT DOWN
COMPARATOR
DROP OUT
DETECTION AMP
AUXILLARY
COMPARATOR
1.23V
16 GND
8 7 6 5
MEMORY ARRAY
128X8 bit/
64X16 bit
HIGH VOLTAGE
GENERATOR
ADDRESS
DECODER
DATA REGISTER
DECODE & CONTROL
LOGIC
CLOCK GENERATOR
2 1 3 4
BUFFER
VCC NC ORG GND
CS SK
DI
DO
U6 KA8602D (BASE MAIN Board)
+ –
2
3
4
BIAS
CIRCUIT
+ –
1
8
7
6
5
AMP1 AMP2
IN+
IN–
OUT1
VCC GND
OUT2
MUTE
RIPPLE
REJECTION