Sony SLV-7700KME, Руководство по обслуживанию

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6-13
Pin No.
Pin Name
I/O
Function
Acti
v
e
“L
” v
er
tical sync r
eset input pin. Pulled-up.
51
XVRST
I
Used for synchr
onizing e
xternal v
er
tical sync and inter
nal v
er
tical sync.
When XVRST is “L”, the internal digital sync generator is reset according to the F1 state. Field ID input pin. W
hen e
xter
nally synchr
onizing with the XVRST signal,
the f
ield to be reset
52
F1
I
is determined by this signal.
“H” indica
tes the f
ir
st f
ield
.
“L
” indicates the second f
ield
.
53
VDD
–
Dig
ital po
wer supply
.
T
est mode contr
ol input pin. Pulled-up.
54
XTEST4
I
When these pins are “H”, CXD1913Q is not s test mode. T
he test mode is allo
wed to use onl
y f
or device v
endor
s.
55
XRST
I
System reset input pin when acti
v
e
“L
”.
During po
wer on/reset, set to “L
” f
or more than 40 c
locks (SYSCLK).
56
SYSCLK
I
System clock input pin. T
o
generate the correct sub carrier fr
equenc
y,
pr
ecisel
y 27 MHz is r
equired.
13.5 MHz pix
el data c
loc
k output pin.
57
PDCLK
O
T
his c
loc
k is obtained by 1/2 fr
equency-di
viding SYSCLK.
Used only in the 16-bit pix
el data mode.
58
VSS
–
Digital GND.
59
VSYNC
O
V
.sync signal output.
60
HSYNC
O
H.sync signal output. The functions of this pin are selected by pin 64 XIICEN.
61
SO
O
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes
the S0 serialout output pin. When the XIICEN pin is “L”, this pin is not used and sets into high impedance. Field ID output. When control r
egister bit
“FDS”=“1”,
“L
” indicates the f
ir
st f
ield and “H”
62
FID
O
indica
tes the second f
ield
.
When control r
egister bit
“FDS”=“0”,
“H”
indicates the f
ir
st f
ield and “L
”
indica
tes the second f
ield
.
63
VDD
–
Dig
ital po
wer supply
.
Serial interface mode selection input pin. Pulled-up.
64
XIICEN
O
W
hen “L
”,
Pins 48 to 50,
and 61 set into the I
2
C-B
US mode.
When “H”, Pins 48 to 50, and 61 set into the SONY SOP mode.