Sony SLV-7700KME, Руководство по обслуживанию

Страница: 91 / 135

6-11
Pin No.
Pin Name
I/O
Function
Composite b
lanking signal pin. Ser
ves as an output w
hen the b
uilt-in
95
CBLNK
I/O
sync generator is used, and as an input when not. /Signal obtained by
/FSC
/O
frequency-di
viding the c
lock input from XTL0I or XTLI.
When the input
clock is 8 fsc, it can be used as the fsc signal. (Not used. open)
96
CSYNC
O
Composite sync signal pin.
A signal is made by fr
equenc
y-di
viding the
DCLK. Cannot be input.
97
XSGRST
I
Sync genera
tor r
eset signal pin. The signal g
enerator is initialized b
y
setting
this pin to ‘L
’.
98
CLK0O
O
Outputs the frequency-di
vided clock of the clock input to XTL0I.
T
he fr
e
quency di
viding r
atio can be selected from 1/2, 1/4, and 1/8.
99
DOUT
O
Digital output. (Not used. open)
1
0
0
D
A
TO
O
Audio serial data output pin. Synchronizes with the clock input from FSXI.
101
LRCO
O
LR clock output pin. Outputs the clock input from the LRCI. (Not used. open)
102
BCK
O
O
Bit clock output pin. Outputs the clock input from the BCKI. (Not used. open)
103
FSXI
I
Input 384fs (16.9344 MHz) or 768fs (33.8688 MHz).
104
VDD
–
+5V po
wer suppl
y.
105
VSS
–
GND.
106
XTL2O
O
CD-R
OM decoder
, audio decoder master c
loc
k. Input a c
loc
k to the XTL2I
or connect an oscillator between XTL2I and XTL2O
.
T
he recommended
107
XTL2I
I
frequency is 45 MHz.
T
his c
lock is for the internal cir
cuit. Does not
synchronise with inputs and outputs.
108
VDD
–
+5V po
wer suppl
y.
109
C2PO
I
C2 pointer input.
110
LRCI
I
LR clock input.
111
D
A
TI
I
Serial data input.
112
BCKI
I
Bit clock input.
113
DOIN
I
Digital input signal.
114
XHCS
I
R
eg
ister access c
hip select signal pin.
115
XHDT
I/O
Data ac
kno
wledg
e/wait signal pin f
or DMA tr
ansmission, r
eg
ister access,
transparent memory access.
116
HR
W
I
Re
gister access contr
ol signal pin.
117
XHIRQ
O
Interrupt request signal.
118
XRST
I
Har
dwar
e reset input pin.
When set to
‘L
’, all re
gister
s and opera
tions ar
e
reset and initialized.
1
1
9
H
A
0
I
A
ddr
ess input pin. In some cases, serv
es as the contr
ol signal and da
ta
120
HA1
I
input according to the setting of the control mode.
Pin No.
Pin Name
I/O
Function
67
R/Cr4
O
68
R/Cr5
O
Output pin of the R or Cr signal of the image data. MSB is R/Cr7.
69
R/Cr6
O
Synchronizes with DCLK.
70
R/Cr7
O
71
G/Y0
O
72
G/Y1
O
Output pin of the G or
Y signal of the image da
ta. MSB is G/Y7.
73
G/Y2
O
Synchronizes with DCLK.
74
VDD
–
+5V po
wer suppl
y.
75
VSS
–
GND.
76
G/Y3
O
77
G/Y4
O
78
G/Y5
O
Output pin of the G or
Y signal of the image da
ta. MSB is G/Y7.
79
G/Y6
O
Synchronizes with DCLK.
80
G/Y7
O
81
B/Cb0
O
82
B/Cb1
O
83
B/Cb2
O
84
B/Cb3
O
Output pin of the B or Cb signal of the image data. MSB is B/Cb7.
85
B/Cb4
O
Synchronizes with DCLK.
86
B/Cb5
O
87
B/Cb6
O
88
B/Cb7
O
Dot clock (DCLK) signal pin.
T
he DCLK frequenc
y is normally
89
DCLK
I/O
13.5 MHz.
The DCLK can be input from this pin or can be made b
y
fr
equenc
y-
di
viding (1/integer) the clock input from XTL0I.
90
VDD
–
+5V po
wer suppl
y.
91
VSS
–
GND. Horizontal sync signal pin.
When using the b
uilt-in sync gener
ator
,
92
HSYNC
I/O
a signal is made by fr
equency-di
viding the dot c
loc
k (DCLK). Ser
ves as
the input w
hen not using the b
uilt-in sync gener
ator
.
V
er
tical sync signal pin.
When using the b
uilt-in sync gener
ator
, a signal
93
VSYNC
I/O
is made b
y
fr
equenc
y-di
viding the DCLK. Ser
v
es as the input when not
using the b
uilt-in sync gener
ator
.
F
ield determina
tion signal signal. Od
d f
ield cor
respond to H and e
v
en
FID
I/O
field correspond to L. Serv
es as an output when the b
uilt-in sync generator
94
/FHREF
/O
is used
, and as an input when not. /Signal obtained by fr
equenc
y-di
viding
the c
loc
k input from XTL0I or XTLI.
When the input clock is 8 fsc,
it can
be used as the horizontal sync signal phase comparison reference signal.