04
6
5
46
8
48
47
45
42
43
44
3
11
12
9
13
4
14
13
23-34, 37-40
D0-D15
D0-D15
A1-A6
CPU
REGISTER
DEVICE
CONTROL
UNIT
END POINT
BUFFER
(3k BYTE FIFO)
USB
PERIPHERAL
CIRCUIT
CLOCK
CONTROL
(OSCILLATOR/
PLL)
USB
TRANSCEIVER
INSTRUCTION
REGISTER
INSTRUCTION
DECODE
CONTROL
&
CLOCK
GENERATION
ADD
BUFFER
/DECODER
DATA
REGISTER
EEPROM
BATTERY
CHARGER
(1/2)
SERIAL
INTERFACE
ENGINE
65-62,59-54,52,50-44
108-105,102-96,94,92-89
157
159
4
156
15
14
25-18,8-1,48
29-36,38-45
115
113
11
6
2
1
3
4
1
2
XWRL
R/W
XLB
XUB
XWRH
OUT
INVERTER
IC711
15
4
1
2
XWRL
XRD
OUT
INVERTER
IC712
14
26
28
4
1
2
XWRH
XRD
OUT
INVERTER
IC713
69
68
73
70
1
71
TRST
DACK
DREQ
CS
INT
RD
WR
RESET
A1-A6
1
1
2
3
4
8
16
18
17
PD31 F SO
XCS2 SRAM XCS
XRD
U XDACK
U XDREQ
XCS3 U XCS
XIRQ7 U XIRQ
XWRLH S XWRH
XWRLL S XWRL
PD28 U XRST
XCS5 F XCS
PD29 F CLK
PD26 F RST
PD30 F SI
5
10
5
D0-D15
A1-A17
A0-A17
16
16
D0-D15
D0-D15
A0-A17
I/O1-I/O16
A0-A16
XCE1 XOE
S-RAM
IC708
MS BS
BS
DIO
INS
SCLK
MS DIO
X701
4MHz
EJECT
MECHANISM
BLOCK
PA19 MS INS
MS CLK
XTAL
EXTAL
X704
12MHz
USB VCC
+3.3V
USB D-
USB D+
D-
D+
TR ON
VBUS
XIN
XOUT
XCS
RESET
DI
XSCK
DO
EEPROM
IC705
SYSTEM CONTROL
IC701(1/3)
UNIVERSAL SERIAL BUS DEVICE CONTROL
IC704
4
16
6
17-22
• SIGNAL PATH
: DIGITAL
4-2. BLOCK DIAGRAM — AUDIO SECTION (1/2) —
– 19 –
– 20 –
NW-MS7
(Page
21)