— 98 —
Pin No.
Pin Name
I/O
Function
1
2
3
4
5
6
7, 8
9, 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PLMG2
VDD
NSDOL4
NSDOL3
NSDOL2
NSDOL1
NC
VDD
NC
64FSI
NSDOR1
NSDOR2
NSDOR3
NSDOR4
MCKIN
VDD
PLMG1
VSS
TEST3
TEST4
DFLRCKO
DFDTOR
NC
MODE
DRPOL
OVFLAG
MUTEL
MUTER
MTPOL
INAF
DINIT
CKVDD
128FSO
NC
INVI
INVO1
INVO2
NC
I
—
O
O
O
O
—
—
—
I
O
O
O
O
I
—
I
—
I
I
O
O
—
I
I
O
O
O
I
O
O
—
O
—
I
O
O
—
4 bit conversion data setting pin in SCD mode (Fixed at “L”)
Power supply (+5V)
Noise shaping data Lch parallel output 4 (MSB) (Not used)
Noise shaping data Lch parallel output 3 (4SB) (Not used)
Noise shaping data Lch parallel output 2 (2SB) (Not used)
Noise shaping data Lch parallel output 1 (LSB) (Not used)
Not used
Power supply (+5V)
Not used
64 Fs clock input
Noise shaping data Rch parallel output 1 (LSB) (Not used)
Noise shaping data Rch parallel output 2 (2SB) (Not used)
Noise shaping data Rch parallel output 3 (4SB) (Not used)
Noise shaping data Rch parallel output 4 (MSB) (Not used)
Master clock input (256 Fs)
Power supply (+5V)
4 bit conversion data setting pin in SCD mode (Fixed at “L”)
Ground
Test pin (Fixed at “L”)
Digital filter data LR clock output
Digital filter data Rch data output
Not used
Mode setting pin
“L”:CD mode, “H”:DSD mode (Fixed at “L”)
Rch data polarity setting pin
“L”:Positive phase (Fixed at “L”)
Digital filter output overflow flag output
“H”:Active (Fixed at “L”)
Mute flag output (Lch) (Not used)
Mute flag output (Rch) (Not used)
Mute flag polarity setting pin
“L”:L active, “H”:H active (Not used)
Sync deviation detection flag
“H”:Active (Sync deviation detection)
External INIT signal delay signal output (Not used)
Power supply (+5V) (Clock system)
128 Fs clock output (Not used)
Not used
384 Fs generation three times buffer input (Not used)
First stage buffer output for three times (Not used)
Second stage buffer output for three times (Not used)
Not used
• IC501 Noise Shaper, Digital Filter (CXD8595Q)/DA board
Содержание MDS-JA50ES / Mode d’emploi
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