HT-XT100
34
L(U)DQM
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decode
r
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Out
put
Buf
fer
Address
Clock
Generator
CLK
CKE
Command Deco
der
CS
RAS
CAS
WE
U14 G527
U10 M12L64164A-7T
NMOS
Switch
Under
Voltage
Lockout
Over-Temperature
Protection
Charge
Pump
Bandgap
Reference
Current
Limit
IN
EN(EN)
GND
SET
OUT
FLAG
Output Reverse-Voltage
Protection
NMOS
Switch
Under
Voltage
Lockout
Over-Temperature
Protection
Charge
Pump
Bandgap
Reference
Current
Limit
IN
EN(EN)
GND
SET
OUT
FLAG
Output Reverse-Voltage
Protection
Содержание HT-XT100
Страница 43: ...MEMO HT XT100 43 ...
Страница 44: ...HT XT100 REVISION HISTORY Ver Date Description of Revision 1 0 2015 02 New ...