Sony HDV HVBK-1505, Японская инструкция по эксплуатации

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4-17 4-17
HVR-1500
KY-616
KY-616 KY-616
100-26 KY-614:103-26
100-24 KY-614:103-24
Q2SD R
Q2SD G
FOR LCD
171
164
KY-614:103-25 100-25
Q2SD B
CPU SCK
100-19 KY-614:103-19
CPU DO
CPU DI
KY-614:103-18 100-18
KY-614:103-20 100-20
KY-614:103-21 100-21
LCD XCS0
KY MPU
IC301
104
165
CS
SK
DI
DO
RDY/BSY
RESET
IC300 EEPROM
4
2
3
1
7
6 184
192
180
10 CS
EEPROM CS
CE2B
DREQ1
MCS4
TXD0
SCK0
RXD0
RESET OUT
100-12
100-11
KY-614:103-12
KY-614:103-11
LCD XHD
LCD XVD
SDIP CK27/8
PLL FCK
KY-614:103-13
KY-614:103-4
KY-614:103-15
KY-614:103-6
KY-614:103-3
HCKX2
HCK1
100-5 KY-614:103-5
HST DRV
HCK X6
PLL FIN
FOR LCD BACK LIGHT
KY-614:103-54 100-54
KY-614:103-50 100-50
LCD LED EN
LCD BRT
115
207
100-53 KY-614:103-53
100-49 KY-614:103-49
FOR AUDIO VR
VR CH1
VR CH2
100-47 KY-614:103-47
VR CH3
100-48
100-46
KY-614:103-48
KY-614:103-46
VR PHONE
VR CH4
199
200
202
201
203
SIRCS VO
KY-614:103-52 100-52
FOR CONTROL S
159
9
PSW C3
KY-614:103-32 100-32
PSW C2
KY-614:103-31 100-31
PSW C1
PSW C0
FOR SW MATRIX
KY-614:103-30 100-30
KY-614:103-29 100-29
113
157
112
107
119
117
118
116
103
PSW R3
PSW R4
KY-614:103-36
KY-614:103-37
100-36
100-37
PSW R2
KY-614:103-35 100-35
PSW R1
PSW R0
KY-614:103-34 100-34
KY-614:103-33 100-33
PSW R6
PSW R5
100-39
100-38
KY-614:103-39
KY-614:103-38
125
126
185
186
188
187
100-40 KY-614:103-40
100-41 KY-614:103-41
FOR LED MATRIX
LED R0
LED R1
100-42 KY-614:103-42
LED R2
100-43 KY-614:103-43
LED R3
100-8 KY-614:103-8
LED PON MASK
KY-614:103-44 100-44
LED R4 182
KY-614:103-59,60
KY-614:103-63,64
100-59,60
100-63,64
+5V-2
A+8.5V
100-65,66 KY-614:103-65,66
100-69,70 KY-614:103-69,70
+1.64V
100-67,68 KY-614:103-67,68
+3V
100-61,62
100-57,58
KY-614:103-61,62
KY-614:103-57,58
-5V
+3V-2
+1.5V
FOR POWER
MONI OUT MUTE
100-73 KY-614:103-73
KY-614:103-78 100-78
KY-614:103-77 100-77
HP L G
HP L X
FOR PHONES
KY-614:103-76 100-76
KY-614:103-75 100-75
PWR-ON
DET
2 1
IC500
+3V
S501
IC503
1
2
4
CPU RESET
XRESET
141
140 Q2SD VSYNCX
Q2SD ODDFX
XPAL 189
13...32 D31-0
26
86... A25-0
RAS3L
CASL 108
106
D31-0
A25-0
RAS3L
CASL
114
DACK0
XDACK0
64MHz
CKIO
162
CLOCK
1
IC406
PLL
2 CPU CLK Q2SD
SDRAM CK 3
7
CPU CLK FPGA 5
2 F
CKE 105
CKE
IC408 IC407
1 5 2 4
1 Q2SD CLK1 OE
Q2SD CLK1
155
XTAL
156
EXTAL
X300
16MHz
IC403
2 102 CS6
CS6
CS0 96 3
CS0
FLASH CS 4
6
5
7 JIG E X
1 JIG ROM ON X
98 FPGA CSX
CS2
99
CS3
101
100
CS5
CS4
90
91
89
93
DQMLU
DQMUL
DQMLL
RD/WR
DQMUU
92
88
RD
191 XDREQ0
Q2SUB INT
8
123
2
IRL
142
JIG EXIST 12
DREQ0
IRL0
WAIT 1
Q2SD XWAIT
Q2SUB XWAIT
4
IC302
FPGA RESET 190
193
RESETP
127 XASEMD0
LD SW 169
ASEMD0
Q2SUB DONE 11
IC507
Q2SD SUB
TEST MODE
DEBUG MODE
S100
D15-0 16 16...
A
DQ
CE
WE
OE
RESET
FLASH ROM
IC402
3
IC202
1
BUFF
145
GRAPHICS RENDERER
IC200
Q2SD
146
BUFF
IC203
IC204
BUFF
148
R
G
B
142
VSYNC
ODDF
155
Q2SD HSYNCX 140
HSYNC
43...
22
A22-1
A22-1
D15-0
CLK0
48
167
DACK
CS1
163
IC205
4
2
1 A25
165
162
WE0
CS0
166
164
WE1
RD
44
169
168
171
RESET
WAIT
DREQ
IRL
16 D15-0
A20-1
20
26
11
28
12
14
A15-2
D31-0 32
IC401
SDRAM
DQ
DQM0
RAS
18
BA,A
19
68
CAS
67
CLK
20
CKE
17
CS
WE
16
71
DQM1
59
28
DQM3
DQM2
JIG
CN401
401-
1
2
4
3
401-
401-
65
42
10
25
401-
NC
+3V
+5V-2
+3.3V
+5V
D15-0
A23-0
16
24
JIG A23-0
JIG D15-0
1
2
4
IC404
A25
CPU IO CS0 X
JIG G X
JIG WR X
MS RESET X
2 4
IC405
88... 8 D7-0
13 174...
A9-0
207
213
90
35
8
10
138
137
12
204
171
39
145
144
70
71
CLK3
Q2SDSUB
IC507
(FPGA)
45
101...
9
47
8
136
132...
137
135
VIN7-0
VQCLK
VODD
VVS
VHS
134 100 Q2SD VHS
Q2SD VVS
Q2SD VQCLK
Q2SD V7-0
Q2SD VODD
IC201 SDRAM
CLK
DQ
BA,A
49
MCLK
MA12-0
MD31-0
32
13
68
MA12-0
MDQ31-0
MCLK
36
139
91
172
38 138 DISP CLK
43
500-14
500-12
500-33
500-4
500-5
500-6
500-7
500-18
500-16
500-36
500-3
500-40
500-41
500-42
500-38
500-43
NC
SSS:52-93
AVP:5-8
AVP:5-7
AVP:5-5
AVP:5-6
AVP:5-9
SSS:51-49
SSS:51-52
SSS:51-50
SSS:51-51
AVP:6-95
AVP:6-96
AVP:6-143
AVP:6-144
DVP:1-9
SSS:52-94
...
21
500- DVP:1-76...
EPR2
CN501
IC505,506
13 7
IC505
8 8
CLK0
77...
7
SDIP DT9-2
SDIP CK27 KY
8
NSG FH
NSG OFOE
17
75
IC506
17
18
3
2
76
19
CHARA SIG
CHARA FRAME 5
4
15
16
IC506
23 SO
IC509
5 3
SCK
SI
80
81 2
5
6
3
1,7 CS 24
67
120
163
160
DCLK
nCSO
ASDO
DATA0
ASDI
DATA
(FLASH)
162
nCE
118
nCONFIG
178
CONF DONE
ASDI
+3V
VCC
DATA OUT
DELAY
Q500
CONFIG START1
IC501,504
IC301 KY MPU
Q2SUB DONE
CONFIG ROM
IC508
CS
LCD XCS0
CPU DI
CPU DO
CPU SCK
CPU SCK
CPU DO
CPU DI
Q2SD R
Q2SD G
Q2SD B
HP R G
HP R X
XRESET
LED PON MASK
LCD XVD
LCD XHD
XRESET
XRESET
CPU RESET
HP R X
HP R G
HP L X
HP L G
MONI OUT MUTE
CS4
CS5
CS3
XRD
DQMUU
RD WR
DQMLL
DQMUL
DQMLU
Q2SD ODDFX
Q2SD VSYNCX
XPAL
XDACK0
CPU CLK Q2SD
Q2SD CLK1
Q2SD CLK1 OE
SDRAM CK
CKE
CPU CLK FPGA
CASL
RAS3L
CS5
CS4
FLASH CS
CS3
JIG E X
CS5
JIG ROM ON X
DQMLU
DQMUL
DQMLL
RD WR
DQMUU
DQMLL
DQMLL
DQMLU
XRD
XRD
XRD
XDREQ0
XIRL
Q2SD XWAIT
FPGA RESET
XRESET
JIG EXIST
XRESET
1 3
1 3
Q2SD ODDFX
Q2SD VSYNCX
Q2SD HSYNCX
Q2SD CLK1
Q2SD CLK1 OE
FPGA CSX
DQMLL
XRD
Q2SUB INT
Q2SUB WAIT
FPGA RESET
DQMLU
SDIP CK27/8
PLL FIN
HCK X6
HCK1
HST DRV
8
A24,23,21
IC502
NSG OFOE
NSG FH
SDIP CK27 KY
SDIP DT9-2
CHARA FRAME
CHARA SIG
KY SY CS
KY SY SI
KY SY SCK
KY SY SO
2
5
1
6
CONF DONE
nCONFIG
nCE
DATA0
ASDO
nCS
DCLK
nCS
nCE
nCONFIG
CONF DONE
DCLK
DCLK
CS
100-13
100-4
100-15
100-6
100-3
401-68
401-80
401-69
401-70
401-9
401-74
401-71
...
...
501-5
501-4
501-2
501-3
501-6
501-9
501-10
501-1
LCD VIDEO PROC