Sony HCD-DX60AV, Руководство по обслуживанию

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50
HCD-DX60AV/RG70AV
5-23. IC PIN FUNCTION DESCRIPTION
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MAIN BOARD IC401 M30622MCA-B43FP (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Description
1
S-OUT
O
Serial data output to the display control (IC701)
2
S-CLK O Serial data transfer clock signal output to the display control (IC701)
3
S-BSY
I
Busy signal input from the display control (IC701) “L”: busy
4
REMOTE-IN
I
Remote control signal input terminal
5 3878-DAT O
Serial data output to the BH3878KS2 (IC301)
6 3878-LAT O
Serial data latch pulse output to the BH3878KS2 (IC301)
7
3878-CLK
O
Serial data transfer clock signal output to the BH3878KS2 (IC301)
8
BYTE I External data bus line byte selection signal input terminal Fixed at “L”: in this set
9 CNVSS
— Ground terminal
10
XCIN I Sub system clock input terminal (32.768 kHz)
11
XCOUT O Sub system clock output terminal (32.768 kHz)
12 RESET
I
System reset signal input from the reset signal generator (IC402) “L”: reset
For several hundreds msec. after the power supply rises, “L”: is input, then it changes to “H”
13 XOUT
O Main system clock output terminal (16 MHz)
14 VSS
— Ground terminal
15 XIN
I Main system clock input terminal (16 MHz)
16 VCC
— Power supply terminal (+5V)
17
NMI I Non-maskable interrupt input terminal Fixed at “H” in this set
18 AC-CUT
I AC off detection signal input from the reset signal generator (IC402) “L”: AC cut checked
19 SCOR
I Subcode sync (S0+S1) detection signal input terminal
20 RDS-INT I
Serial data transfer clock siganl input terminal Used for the AEP model only
21 RDS-DATA I
Serial data input terminal Used for the AEP model only
22 ST-MUT O
Tuner muting contorl signal output terminal “H”: muting on
23 STEREO
I FM stereo detection signal input from the FM/AM tuner system (IC101) “L”: stereo
24 TUNED
I Tuning detection signal input from the FM/AM tuner system (IC101) “L”: tuned
25
ST-CE O PLL chip enable signal output to the PLL (IC102)
26 ST-DOUT
O PLL serial data output to the PLL (IC102)
27
ST-DIN
I
PLL serial data input from the PLL (IC102)
28
ST-CLK O PLL serial data transfer clock signal output to the PLL (IC102)
29
IIC-CLK I/O Shift clock signal input/output terminal for the IIC bus Fixed at “H” in this set
30
IIC-DAT I/O Data input/output terminal for the IIC bus Fixed at “H” in this set
31
CAN' T-USE — Not used (open)
32
SQ-DAT IN I Subcode Q data input terminal
33
SQ-CLK O Subcode Q data reading clock signal output terminal
34
SENS (CXD2587
SENS)
I Internal status (SENSE) signal input from the CXD2587Q (IC101)
35
CD-DAT OUT O Serial data output to the CXD2587Q (IC101)
36
CAN' T-USE — Not used (fixed at “L”)
37
CD-CLK O Serial data transfer clock signal output to the CXD2587Q (IC101)
38
CD-POWER O CD power on/off control signal output “L”: on, “H”: off
39 (CLOCK-OUT)
— Clock signal output terminal Not used (open)
40
HOLD O Laser power control signal output to the CXA2568M (IC103)
41
M-RESET O Micom reset signal output to the display control (IC701) “L”: reset
42
XLT (CD) O Serial data latch pulse output to the CXD2587Q (IC101)
43
XRST (CD) O CD reset signal output to the CXD2587Q (IC101) and BA5974FP (IC102) “L”: reset