56
HCD-DP700
• IC601 DECODER (CXD9617R) (DSP Board (1/2))
Function
Pin Name
Pin No.
I/O
1
VSS
—
Ground
2
XRST
I
Reset signal input
3
EXTIN
I
GND
4
FS2
I
Sampling frequency switching signal input
5
VDDI
—
Power supply
6
FS1
I
Sampling frequency switching signal input
7
PLOCK
O
Internal PLL lock signal output
8
VSS
—
Ground
9
MCLK1
I
Clock signal input (135 MHz)
10
VDDI
I
Power supply
11
VSS
—
Ground
12
MCLK2
I/O
13
MS
I
Switching of master/slave operation 0 : internal clock, 1 : EXTIN clock is used
14
SCKOUT
O
Internal system clock signal output
15
LRCKI1
I/O
Sampling clock input/output for audio IF serial data (Not used)
16
VDDE
—
Power supply
17
BCKI1
I/O
Bit clock input/output terminal for audio IF serial data (Not used)
18
SDI1
I
Audio IF data input
19
LRCKO
O
Sampling clock output for audio IF serial data
20
BCKO
O
Bit clock output terminal for audio IF serial data
21
VSS
—
Ground
22
KFSIO
I/O
Audio clock signal (364fs/256fs) input/output
23 - 26
SDO1 - SDO4
O
Audio IF serial data output
27
SPDIF
O
S/D IF output (Not used)
28
LRCKI2
I
Sampling clock input for audio IF serial data
29
BCKI2
I
Bit clock input terminal for audio IF serial data
30
SDI2
I
Audio IF data input
31
VSS
—
Ground
32
HACN
O
Acknowledge signal output for host IF
33
HDIN
I
Serial data input for host IF
34
HCLK
I
Clock input for host IF
35
HDOUT
O
Serial data output for host IF
36
HCS
I
Chip select input for host IF
37
SDCLK
O
SDRAM clock output (Not used)
38
CLKEN
O
SDRAM clock enable signal output (Not used)
39
RAS
O
Raw address strobe signaloutput (Not used)
40
VDDI
—
Power supply
41
VSS
—
Ground
42
CAS
O
Column address strobe output (Not used)
43
DQM/OE0
O
Data input /output mask signal output (Not used)
44
CS0
O
External memory chip select (SRAM)
45
WE0
O
SRAM write enable output
46
VDDE
—
Power supply
47
WMD1
I
External memory wait mode signal input
48
VSS
—
Ground
49
WIMD0
I
External memory wait mode signal input
50
PAGE2
O
External memory page switching signal output
51
VSS
—
Ground
52
PAGE1
O
External memory page switching signal output (Not used)
53
PAGE0
O
External memory page switching signal output
54
BOOT
I
Boot mode control signal input
55
BTACT
O
Boot mode state display signal output (Not used)
56
BST
I
Boot stop signal input
57
MOD1
I
Operation mode signal input (L : 386fs, H : 256fs)
Содержание HCD-DP700
Страница 37: ...37 37 HCD DP700 6 15 SCHEMATIC DIAGRAM FRONT AMP SECTION AEP US CND model Page 50 Page 30 Page 30 ...
Страница 39: ...39 39 HCD DP700 6 17 SCHEMATIC DIAGRAM FRONT AMP SECTION E51 MX model Page 50 Page 30 Page 30 Page 40 ...
Страница 40: ...HCD DP700 40 40 6 18 SCHEMATIC DIAGRAM SURROUND AMP SECTION Page 30 Page 39 Page 50 ...
Страница 44: ...HCD DP700 44 44 6 22 SCHEMATIC DIAGRAM PANEL 2 2 SECTION Page 43 Page 43 ...
Страница 46: ...HCD DP700 46 46 6 24 SCHEMATIC DIAGRAM LEAF SW SECTION Page 29 ...
Страница 48: ...HCD DP700 48 48 6 26 SCHEMATIC DIAGRAM DRIVER SECTION See page 61 for IC Block Diagrams Page 29 ...