Sony DMP-1000P, Руководство по обслуживанию, Страница: 52 / 79

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DMP-1000P (AEP)
Pin No. Pin Name I/O Description
94 MNT2 O Test monitor output terminal (normally: open)
95 MNT1 O Test monitor output terminal (normally: open)
96 DVCC — Power supply terminal (+5V) (logic system)
97 PCSX O Chip select signal output to the mechanism controller (IC505)
98 DCSX O Chip select signal output terminal Not used (open)
99 SVW I Data write end latch pulse input from the system controller (IC503)
100 VRSR I Refresh stop request input from the system controller (IC503)
101 DGND — Ground terminal (logic system)
102 SVBK O V blanking interrupt signal output to the system controller (IC503)
103 STRS O Busy signal output to the system controller (IC503)
104 BSH O
Status (CPU emancipation of memory bus) output to the system controller (IC503)
105 SRDX I
Data read enable signal input from the system controller (IC503)
106 SWEX I
Data write enable signal input from the system controller (IC503)
107 SC6X I
Chip select signal input from the system controller (IC503)
108 SHWX O
CPU D-RAM access wait control signal output to the system controller (IC503)
109 SRSX I
Row address strobe signal input from the system controller (IC503)
110 SCSX I
Column address strobe signal input from the system controller (IC503)
111 DGND —
Ground terminal (logic system)
112 DVCC —
Power supply terminal (+5V) (logic system)
113 ICKI I
System clock signal (for INT SG) input from the system controller (IC503)
114 ICKO O
System clock signal output terminal Not used (open)
115 XGND —
Ground terminal (crystal system)
116 XOUT O
System clock signal output terminal Not used (open)
117 XIN I
System clock signal input terminal Not used (fixed at “L”)
118, 119 DGND —
Ground terminal (logic system)
120 SADB I
Address signal input for the chip select signal generate Connected to address bus (A14)
121 SADA I
Address signal input for the chip select signal generate Connected to address bus (A13)
122 DGND —
Ground terminal (logic system)
123 MRSX O
Row address strobe signal output to the D-RAM (IC403)
124 MCSX O
Column address strobe signal output to the D-RAM (IC403)
125 MWEX O
Write enable signal output to the D-RAM (IC403)
126 DVCC —
Power supply terminal (+5V) (logic system)
127 to138 SAD11 to SAD0 I
Address signal input from the system controller (IC503)
139 DGND —
Ground terminal (logic system)
140 to147 SDT15 to SDT8 I/O
Two-way data bus with the system controller (IC503), mechanism controller (IC505) and
D-RAM (IC509) (upper 8 bit)
148 DGND —
Ground terminal (logic system)
149 DVCC —
Power supply terminal (+5V) (logic system)
150 to157 SDT7 to SDT0 I/O
Two-way data bus with the system controller (IC503), mechanism controller (IC505), flash
memory (IC506), D-RAM (IC509) and floppy disk drive controller (IC2101) (lower 8 bit)
158 DGND —
Ground terminal (logic system)
159 DVCC —
Power supply terminal (+5V) (logic system)
160 to167 MDT0 to MTD7 I/O
Two-way data bus with the D-RAM (IC403) (lower 8 bit)
168 DGND —
Ground terminal (logic system)
169 DVCC —
Power supply terminal (+5V) (logic system)
170 to176 MDT8 to MTD14 I/O
Two-way data bus with the D-RAM (IC403) (upper 8 bit)