22
D-CJ500/CJ501/CJ506CK
• MAIN Board IC701 CXD9717R-002 (MP3 Decoder)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 38
39
40
41
42
43 to 44
45
46, 47
48
49 to 51
52
53
54
55
56
57
58
59
I/O
I
I
I
I
I/O
I
O
—
O
O
O
I
I
I
I
I
I
—
I
—
—
—
O
—
—
O
—
—
I
O
O
—
O
O
—
I/O
—
I
—
I/O
—
I/O
—
I/O
I
I
—
O
I
—
Pin Name
/RESET
MIMD
/MICS
/MILP
MIDIO
/MICK
MIACK
VDDT
SDO
BCKO
LRCKO
SDI0
BCKIA
LRCKIA
SDI1
BCKIB
LRCKIB
VDD
STANDBY
VSS
VSSL
VRAL
LO
VDAL
VDAR
RO
VRAR
VSSR
TESTP
TX0
PO0 to PO3
VDDT
PO4 to PO6
PO7
VSS
AD13
VDDM
FI0 to FI1
VSSM
IO0,IO1
VSS
IO2 to IO4
VDD
IO5
TSTIN
FI2
VSSP
PDO
VCOI
VDDP
Description
Reset input terminal “L”: reset
Microcomputer interface mode selection input “H”: I2C, “L”: TSB
Microcomputer interface chip select signal input (fixed at “L”)
Microcomputer interface latch pulse input (fixed at “L”)
Microcomputer interface serial data input/output (SDA in I2C mode)
Microcomputer interface serial clock input (SCL in I2C mode)
Microcomputer interface acknowledge signal output (open)
Power supply (3.3V) for digital circuit
Data output
Bit clock output (open)
LR clock output (open)
Data input 0
Bit clock input A
LR clock input A
Data input 1 (fixed at “L”)
Bit clock input B (fixed at “L”)
LR clock input B (fixed at “L”)
Power supply (2.5V) for digital circuit
Standby mode control signal input “H”: STB, “L”: normal
Ground for digital circuit
Ground for DAC Lch
Reference voltage terminal for DAC Lch
DAC Lch signal output (open)
Power supply (2.5V) for DAC Lch
Power supply (2.5V) for DAC Rch
DAC Rch signal output (open)
Reference voltage terminal for DAC Rch
Ground for DAC Rch
Terminal for test “H”: test mode, “L”: normal (fixed at “L”)
SPDIF signal output (open)
Genaeral purpose output 0 to 3 (open)
Power supply (3.3V) for digital circuit
Genaeral purpose output 4 to 6 (open)
Genaeral purpose output 7 Interrupt request signal output to the system control (IC801)
Ground for digital circuit
External interrupt signal input (fixed at “L”)
Power supply (2.5V) for internal 1Mbit SRAM
Flag signal input 0 to 1
Ground for internal 1Mbit SRAM
External DRAM data input/output (fixed at “L”)
Ground for digital circuit
External DRAM data input/output (fixed at “L”)
Power supply (2.5V) for digital circuit
External DRAM data input/output (fixed at “L”)
Test terminal (fixed at “L”)
Flag signal input 2 (fixed at “L”)
Ground for VCO circuit
PLL phase error detection signal output
VCO control voltage input
Power supply for VCO circuit (2.5V)
