10
10
D-CJ500/CJ501/CJ506CK
5-1. Block Diagram – MAIN-1 Section –
• R-ch is omitted due to
same as L-ch.
• Signal path
:CD
:CD-R/RW(MP3)
86
87
17
40
46
55
42
16
XSOE_O
GRSCOR_INT
FOK_I
GFS_I
SCOR_INT
SENS
SCK
XLA
T
35
36
13
14
61
OPTICAL PICK-UP
BLOCK
DAX-25E
A
A
B
RF
E
F
B
RF
E
F
PD
PD
LD
LD
DETECTOR
VCC
FOCUS
COIL
TRACKING
COIL
FI2
RI2
33
34
FI1
RI1
FI3
VINDET
RI3
15
PWM/FI4
16
PDL/RI4
APCREF
VCC1 +2V
FO2
RO2
FO3
RO3
RF2
INM2
RF21
PAPC
F+
F–
T+
T–
IC403
COMPARATOR
SYNC
83 STB_RW_O
95
100
51
AMUTE_O
82
XQOK_O
89
XWRE_O
53
96
XRST_O
92
XRDE_O
49
XAPCOFF_O
44
BEEP_O
MP3_DSP_RST
SDA0(I2C)
SCL0(I2C)
ST
ANDBY_O
MP3DSP_I
SDTO
SCK
IC801 (1/2)
SYSTEM CONTROL
X601
16.9MHz
B
C
A
28
26
23
21
63
64
59
M901
SPINDLE
MOTOR
FO4
RO4
M
C+
C–
19
17
DRIVER
DRIVER
CONTROLLER
DRIVER
PD AMP
LD AMP
Q404,405
LD
DRIVER
LEVEL
SHIFTER
60
IC401 (1/2)
FOCUS/TRACKING COIL DRIVER,
SPINDLE/SLED MOTOR DRIVER
B+ +3V
62
M902
SLED
MOTOR
FO1
RO1
M
S+
S–
32
30
DRIVER
IC601
RF AMP,
DIGITAL SIGNAL PROCESSOR,
DIGITAL SERVO PROCESSOR,
D-RAM CONTROLLER
LPF
SIGNAL
PROCESSOR
BLOCK
MEMORY
CONTROLLER,
BUS BOOST
BLOCK
SERVO
BLOCK
MDS
MDP
SENS
SCOR
SDTO
XTAO
XRDE
XTAI
RFAC
XSOE
XLAT
CLOK
XRAS
XWE
XCAS
AOUT2
AOUT1
LRMU
XRST
/RESET
MIDIO
/MICK
ST
ANDBY
PO7
RFDC
B
A
SFDR
SRDR
FFDR
FRDR
TFDR
TRDR
D0-D3
D0-D3
A0-A10
A0-A10
WDCK
GFS
XTAO
XTAI
E
F
89
F
92
91
A
B
88
84
RFDC
RFAC
E
90
5
4
23
IC602
D-RAM
XRAS
XWE
XCAS
100
99
SFDR
SRDR
96
95
FFDR
FRDR
98
97
TFDR
TRDR
26
24
22
65
23
20
102
MDS
103
MDP
27
SCOR
104
C176
FOK
XSOE
WDCK
SENS
CLOK
XLA
T
69
GFS
25
SYSM
30
XQOK
31
XWRE
61
28
51
56
48
9
2
1
47
R-CH
R-CH
LIN
IC301
HEADPHONE AMP
14
LOUT
8
PWRSW
MUTE
19
BEEP
17
PW SW
BEEP
MT SW
20
VOLUME
RV301
J301
i
4, 3,
6, 5
2, 3,
24, 25
116-113,
17-15,
13-11,
117
19-12,
15-19,
21,8
OPGSW
OPSTB
OPGSW
OPSTB
OPGSW
OPSTB
1
3
4
41
SDTO
21
SDTO
1
7
3
5
6
2
3
5
1
7
IC804
BUFFER
IC803
BUFFER
R-CH
9
109
107
111
60
62
39
1
12
108
14
106
13
110
18
7
3
IC701
MP3 DECODER
PCMD_I
PCMD_O
LRCK_I
LRCK_O
BCK_I
BCK_O
45
5
47
6
1
98
19
SDO
SDI0
LRCKIA
BCKIA
CKO
XI
Q701
IC703
BUFFER
1
7
3
5
6
2