21
D-CJ500/CJ501/CJ506CK
Pin No.
107
108
109
110
111
112
113 to 116
117
118
119 to 120
I/O
I
O
I
O
I
—
O
O
O
O
Pin Name
LRCK_I
PCMD_O
PCMD_I
BCK_O
BCK_I
DVDD
A3 to A0
A10
A11
A12,A13
Description
D/A interface LR clock input
D/A interface Serial data output
D/A interface Serial data input
D/A interface Bit clock output
D/A interface Bit clock input
Power supply (DRAM interface)
DRAM address bus 3 to 0
DRAM address bus 10
DRAM address bus 11 Not used (open)
Test pin Not used (open)
