SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 3
Version 2.0
Table of Content
AMENDENT
HISTORY ................................................................................................................................................................. 2
1
11
PRODUCT OVERVIEW ......................................................................................................................................................... 6
1.1
FEATURES ....................................................................................................................................................................... 6
1.2
SYSTEM
BLOCK
DIAGRAM ......................................................................................................................................... 7
1.3
PIN
ASSIGNMENT .......................................................................................................................................................... 7
1.4
PIN
DESCRIPTIONS ........................................................................................................................................................ 8
1.5
PIN
CIRCUIT
DIAGRAMS .............................................................................................................................................. 9
2
22
CENTRAL PROCESSOR UNIT (CPU) ............................................................................................................................... 12
2.1
PROGRAM
MEMORY
(ROM) ...................................................................................................................................... 12
2.1.1
RESET VECTOR (0000H) .................................................................................................................................... 13
2.1.2
INTERRUPT VECTOR (0008H) .......................................................................................................................... 14
2.1.3
LOOK-UP TABLE DESCRIPTION ..................................................................................................................... 16
2.1.4
JUMP TABLE DESCRIPTION ............................................................................................................................. 18
2.1.5
CHECKSUM CALCULATION ............................................................................................................................ 20
2.2
DATA
MEMORY
(RAM) ............................................................................................................................................... 21
2.2.1
SYSTEM REGISTER ............................................................................................................................................ 21
2.2.1.1
SYSTEM REGISTER TABLE ......................................................................................................................... 21
2.2.1.2
SYSTEM REGISTER DESCRIPTION ............................................................................................................ 21
2.2.1.3
BIT DEFINITION of SYSTEM REGISTER .................................................................................................... 22
2.2.2
ACCUMULATOR ................................................................................................................................................. 24
2.2.3
PROGRAM FLAG ................................................................................................................................................ 25
2.2.4
PROGRAM COUNTER ........................................................................................................................................ 26
2.2.5
H, L REGISTERS .................................................................................................................................................. 29
2.2.6
Y, Z REGISTERS .................................................................................................................................................. 30
2.2.7
R REGISTER ......................................................................................................................................................... 30
2.3
ADDRESSING
MODE ................................................................................................................................................... 31
2.3.1
IMMEDIATE ADDRESSING MODE .................................................................................................................. 31
2.3.2
DIRECTLY ADDRESSING MODE ..................................................................................................................... 31
2.3.3
INDIRECTLY ADDRESSING MODE ................................................................................................................. 31
2.4
STACK
OPERATION ..................................................................................................................................................... 32
2.4.1
OVERVIEW .......................................................................................................................................................... 32
2.4.2
STACK REGISTERS ............................................................................................................................................ 33
2.4.3
STACK OPERATION EXAMPLE ....................................................................................................................... 34
2.5
CODE
OPTION
TABLE ................................................................................................................................................. 35
2.5.1
Fcpu code option .................................................................................................................................................... 35
2.5.2
Reset_Pin code option ............................................................................................................................................ 35
2.5.3
Security code option ............................................................................................................................................... 35
3
33
RESET...................................................................................................................................................................................... 36
3.1
OVERVIEW .................................................................................................................................................................... 36
3.2
POWER
ON
RESET ........................................................................................................................................................ 37
3.3
WATCHDOG
RESET ..................................................................................................................................................... 37
3.4
BROWN
OUT
RESET .................................................................................................................................................... 37
3.5
THE
SYSTEM
OPERATING
VOLTAGE ...................................................................................................................... 38
3.6
LOW
VOLTAGE
DETECTOR
(LVD) ........................................................................................................................... 38
3.7
BROWN
OUT
RESET
IMPROVEMENT ...................................................................................................................... 40
3.8
EXTERNAL
RESET ....................................................................................................................................................... 41
3.9
EXTERNAL
RESET
CIRCUIT ...................................................................................................................................... 41
3.9.1
Simply RC Reset Circuit ........................................................................................................................................ 41
3.9.2
Diode & RC Reset Circuit ...................................................................................................................................... 42
3.9.3
Zener Diode Reset Circuit ...................................................................................................................................... 42
3.9.4
Voltage Bias Reset Circuit ..................................................................................................................................... 43
3.9.5
External Reset IC ................................................................................................................................................... 43
4
44
SYSTEM CLOCK ................................................................................................................................................................... 44
4.1
OVERVIEW .................................................................................................................................................................... 44
4.2
F
CPU
(INSTRUCTION
CYCLE) ..................................................................................................................................... 44
4.3
SYSTEM
HIGH-SPEED
CLOCK ................................................................................................................................... 44
4.3.1
HIGH_CLK CODE OPTION ................................................................................................................................ 45
4.3.2
INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC) ........................................................................... 45
