![Solution Systems CompactPCI CPV5370-700-01 Скачать руководство пользователя страница 57](http://html1.mh-extra.com/html/solution-systems/compactpci-cpv5370-700-01/compactpci-cpv5370-700-01_installation-and-reference-manual_1317080057.webp)
3-12
Computer Group Literature Center Web Site
Functional Description
3
SOFTRST (Bit 5)
Use this bit to change the Watchdog Reset function to Soft reset. Refer to
. This bit clears on power-up reset.
ALARM_EN (Bit 6)
This bit controls whether an FPGA alarm generates on a watchdog timeout
event.
❏
Write a logic 1 to cause an alarm signal to become active on a
watchdog timeout event.
❏
Write a logic 0 to cause the alarm signal not to become active on a
watchdog timeout event.
❏
Read this bit to return the last written value.
CLR_STATUS (Bit 7)
Use this bit to reset the watchdog timer output latch.
❏
Write a logic 1 to hold the watchdog timer output latch in a reset
state.
❏
Write a logic 0 to permit a watchdog timer event to be latched.
Reading this bit returns the last written value.
Table 3-10. SOFT_RST bit 5 settings
Set bit to:
For:
0 (default)
hard reset
1
soft reset
Solution Systems Technologies Inc.
720-565-5995 | [email protected] | www.solusys.com
Solution Systems Technologies Inc.
720-565-5995 | [email protected] | www.solusys.com