SMART Embedded Computing MC1600, Инструкция по установке и эксплуатации

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System Overview
MC1600 Extreme Edge Server Installation and Use (6806870A02B) 63
The SyncE PLL has a free-running oscillator that can be used to generate a reference clock
when no recovered clock is available. When it is desired to use a recovered clock, the ports
used for primary and secondary clock recovery can be set up in the control registers of the
Ethernet switch. The primary and secondary recovered clocks go to the input multiplexer
of the SyncE PLL. The clock valid signals go to the input selection logic of the SyncE PLL
chip. In addition, the SyncE PLL chip has internal monitoring circuits to evaluate the quality
of the incoming clocks, and it can be set up for hitless, automatic switching between the
primary and secondary recovered clocks. It also supports holdover mode in case the
recovered clocks are temporarily lost.
The SyncE PLL can store up to four configurations (0-3). By default, configuration 0 is the
only one programmed and is loaded at power-on. Other configurations (1 - 3) could be
programmed into the device and selected via a register in the Glue CPLD. Upon the next
payload reset, the selected configuration would be loaded. The Glue CPLD retains this
selection as long as management power is present.
1.8.3.2 IEEE 1588 Support
The Ethernet switch has time-stamping capability with support for IEEE 1588 1-step and
2-step transparent clock. No external hardware is required.
1.9 PCIe Slot
The Extreme Edge Server base board has a x16 PCIe right-angle connector that can
accommodate a standard or custom PCIe add-in card up to full height, 3/4 length.
Additional physical height is available beyond 0.8" if a customer application needs
additional heat sink height.
Connector lanes are routed as:
 Lane 7:0 to PCIe 3.0 port of CPU1
 Lanes 15:8 to PCIe 3.0 port of CPU2
Because of this routing, a standard PCIe add-in card with a single port can only connect to
CPU1, with a maximum link width of x8.
A custom PCIe add-in card with multiple ports on the PCIe connector can connect to both
CPUs. For example, a custom card may have x16 card edge, bifurcated into two x8 ports.
In this case, it can connect to CPU1 and CPU2, each with a maximum link width of x8. Refer
to
Figure 1-5 , High Level Broadwell-DE Block Diagram on page 53 .