SLE SLE2000 HFO, Руководство по обслуживанию, Страница: 9 / 84

SLE2000 HFO Service Manual
Doc No. SM/0001: Issue 7.0
Page 9 of 84
3.1.1 F
RONT
P
ANEL
B
OARD
A
SSEMBLY
(A0700/02)
This board is mounted behind the front panel of the SLE2000 HFO Electronic unit and is above the
A0701/02 board. On this board are the seven segment LED displays for; BPM, INSP, I:E, PRESSURE
and FIO
2
. There are two discreet LED’s on this board for Power (green) and System Fail (red).
3.1.2 LED D
ISPLAY
B
OARD
A
SSEMBLY
(A0701/02)
This board is mounted behind the front panel of the SLE2000 HFO Electronic unit and is below the
A0700/02 board. It has a single logic device which is used to drive the max, min and mean LED’s next to
the pressure display switch.
3.1.3 V
ENTILATOR
CPU B
OARD
A
SSEMBLY
(A0702/02)
The processor (U14) is an 80C31 microcontroller running at 11.0592MHz. It is an 8 bit processor,
employing time multiplexed address and data operations. Software is provided by the ROM (U6).
Analogue input parameters from panel control settings (BPM rate, inspiration time and high pressure are
converted to digital 8 bit words by the ADC (U18) which scans each input in turn. Open circuit input fault
conditions are detected by software and pull-up resistor array (RU3). Switched input parameters (Mode,
Reset, Mute and Pressure display Mode) are scanned by (U12).
Confirmation of correct solenoid valve energisation voltages is fed to (U14/14) by potential divider R34,
R32 and clamp D3.
Supply voltage supervisor (U7) will attempt to reset the processor (U14/9) should the logic supply voltage
(5.12V dc) fall below (4.8V dc). It also holds the processor reset for a 2 second test period on power up.
Trigger back-up and alarm mute indication LED's are driven by the processor from (U14/5) and (U14/7)
via buffer (U10) and are connected to PLB3a and PLB 15b.
The main PIP solenoid and the waveshape solenoid valve are driven from (U14/8) via buffer (U10) and
MOS driver Q4.
(U1) and (U2) are 7 segment display drivers.
There is a supervisory watchdog alarm system which consists of (U8) and (U3) and BZ2. This monitors a
train of pulses of 20ms period from the processor (U14/3 - the port is toggled every 10ms) to confirm the
correct running of the software. A disruption of these pulses will activate a latched audible alarm BZ2. In
addition, reset pulses from (U7/6) to (U14/9) will attempt to restart the software until the watchdog pulses
are restored.
The Mains Failure Alarm relay-RLl is energised from the 5.12 volt logic supply and holds pins 1 and 14
open. Should the relay de-energise contacts 1 and 14 will close, and a battery powered alarm will be
activated via connections PLB 18a and PLB 20a.