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SiT6503EB HW UM Rev. 1.01
Page 11 of 35
SiT6503EB Evaluation Board (EVB) HW User Manual
Figure 7. Output Clock Termination Circuit
12.1
Output Differential Termination
LVDS (default configuration), LVPECL, HCSL, and CML differential signaling types can be supported by
changing the output termination circuits.
12.1.1
LVDS, CML
The board is shipped to support LVDS, CML in its default differential. The signals are ac coupled with
ceramic 0.1 uF capacitors instead of the corresponding series resistors RSExx (Refer to
) which
are not populated.
Table 7. Output Port RSExx Resistors
Output Port #
0
1
2
3
4
5
6
7
8
9
10
0.1 uF
capacitors
RSE21
RSE22
RSE17
RSE19
RSE1
RSE5
RSE2
RSE6
RSE4
RSE7
RSE3
RSE8
RSE10
RSE14
RSE9
RSE13
RSE11
RSE15
RSE12
RSE16
RSE18
RSE20
Output termination resistors as shown in