SiTime SiT6503EB, Руководство пользователя, Страница: 10 / 35

SiT6503EB HW UM Rev. 1.01 Page 10 of 35 www.sitime.com
SiT6503EB Evaluation Board (EVB) HW User Manual
11
Clock Inputs
The SiT6503EB has eight inputs (4 differential pairs) with SMA connectors (IN0_P, IN0_N, IN1_P, IN1_N,
IN2_P, IN2_N, IN3_P, IN3_N) for receiving external clock signals. All input clocks are ac-coupled and
50

terminated as shown in Figure 6 below. This represents four differential input clock pairs. Single-
ended clocks can be used by driving the ‘P’ side of the differential pair with the ‘N’ input floating.
Figure 6 shows the Input Clock Termination Circuit for one of the 4 pairs.
Figure 6. Input Clock Termination Circuit
12
Clock Outputs
When shipped from factory, each of the twenty output drivers (10 differential pairs) is ac-coupled to its
respective SMA connector – this is the default configuration. The output clock termination circuit is
shown in
Figure 7 below. If dc coupling is required, the corresponding 0.1 uF ac coupling capacitor can
be replaced with a zero

resistor. Figure 7 shows Output Clock Termination Circuit for one of the 10
output pairs.