6. Clock Input Circuits (INx/INxB)
The Si5396J-A-EVB has eight SMA connectors (IN0/IN0B–IN3/IN3B) for receiving external clock signals. All input clocks are terminated
as shown in
Figure 6.1 Input Clock Termination Circuit on page 8
below. Note input clocks are ac-coupled and 50 Ω terminated. This
represents four differential input clock pairs. Single-ended clocks can be used by appropriately driving one side of the differential pair
with a single-ended clock. For details on how to configure inputs as single-ended, please refer to the Si5396 data sheet. Typically a
0.1 μF dc block is sufficient, however, 10 μF may be needed for lower input frequencies. Note that the EVB is populated with both dc
block capacitor values.
Figure 6.1. Input Clock Termination Circuit
UG336: Si5396 Evaluation Board User's Guide
Clock Input Circuits (INx/INxB)
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