Your configuration’s design report will appear in a new window, as shown below. Compare the observed output clocks to the frequen-
cies and formats noted in your default project’s Design Report.
Figure 10.12. Design Report Window
10.4.2 Verify Locked Mode Operation
Assuming you connect the correct input clocks to the EVB (as noted in the Design Report shown above), the DUT on your EVB will be
running in “locked” mode.
UG336: Si5396 Evaluation Board User's Guide
Using the Si5396J-A-EVB
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