6. Clock Input Circuits (INx/INxB and FB-IN/FB-INB)
The Si5372-EVB has four SMA connectors (IN0/IN0B and IN1/IN1B) for receiving external clock signals. All input clocks are terminated,
as shown in the figure below.
Input clocks are ac-coupled and 50 Ω terminated. This represents four differential input clock pairs. Single-ended clocks can be used by
appropriately driving one side of the differential pair with a single-ended clock. See the Si5372 data sheet for details on how to config-
ure inputs as single-ended.
Figure 6.1. Input Clock Termination Circuit
UG372: Si5372 Evaluation Board User’s Guide
Clock Input Circuits (INx/INxB and FB-IN/FB-INB)
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