Silicon Laboratories Si5372, Руководство пользователя

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1. Functional Block Diagram
A functional block diagram of the Si5372-EVB is shown below. Keep in mind the J grade does not use an external XTAL or reference
and does not use the XA/XB pins. This EVB can be connected to a PC via the main USB connector for programming, control, and
monitoring. See or Section
2. Quick Start for more information.
Si5372
OUT_0
OUT_0B
Output
Termination
OUT_1
OUT_1B
Output
Termination
OUT_2
OUT_2B
Output
Termination
OUT_3
OUT_3B
Output
Termination
48 MHz
XTAL
Input
Termination
Input
Termination
XA
XB
IN_0
IN_0B
IN_1
IN_1B
Power Supply
C8051F380
MCU
+
Peripherals
I2C/SPI Bus
VDDO_0
VD
D_Cor
e
VDD_3.3
VDDO_1 VDDO_2 VDDO_3
VDDO_0 VD
D_Cor
e
VDD_3.3 VDDO_1 VDDO_2 VDDO_3
Main USB
Connector
Ext +5V
Connector
I2C/SPI Bus
+5V_USB
+5V_Ext
VDDMCU
Input Clock 0
{
Input Clock 1
{
}
Output Clock 0
}
Output Clock 1
}
Output Clock 2
}
Output Clock 3
Power only
Control/
Status
INTR
Alarm_Status
Figure 1.1. Si5372-EVB Functional Block Diagram
UG372: Si5372 Evaluation Board User’s Guide
Functional Block Diagram
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