S i 4 4 3 0
18
Preliminary Rev. 0.4
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si4430 communicates with the host MCU over a 3 wire SPI interface: SCLK, SDI, and nSEL. The host MCU
can also read data from internal registers on the SDO output pin. A SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA),
as demonstrated in Figure 2. The 7-bit address field supports reading from or writing to one of the 128, 8-bit control
registers. The R/W select bit determines whether the SPI transaction is a write or read transaction. If R/W = 1, it
signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are
latched into the Si4430 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 10.
The SCLK rate is flexible with a maximum rate of 10 MHz.
Figure 2. SPI Timing
To read back data from the Si4430, the R/W bit must be set to 0 followed by the 7-bit address of the register from
which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight negative
edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the
selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After the READ
function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit
clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
Table 10. Serial Interface Timing Parameters
Symbol
Parameter
Min (nsec)
Diagram
t
CH
Clock high time
40
t
CL
Clock low time
40
t
DS
Data setup time
20
t
DH
Data hold time
20
t
DD
Output data delay time
20
t
EN
Output enable time
20
t
DE
Output disable time
50
t
SS
Select setup time
20
t
SH
Select hold time
50
t
SW
Select high period
80
nSEL
SCLK
SDI
MSB
LSB
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1
D0
A4
xx
xx
A3
RW A7
A6
A5
RW
Data
Address
SDI
SCLK
SDO
nSEL
t
CL
t
CH
t
DS
t
DH
t
DD
t
SS
t
EN
t
SH
t
DE
t
SW
