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Silicon Laboratories EM3585 Скачать руководство пользователя страница 16

E M 3 5 8 x

Table 6.1. EM358x Pin Descriptions (Continued)

46

Rev 1.0

Pin #

Signal

Direction

Description

33

PC2

I/O Digital

I/O

Enable with GPIO_DBGCFG[5] and GPIO_PCCFGH[1] clear

JTDO

O

JTAG data out to debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)

SWO

O

Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[11:8]
Enable Serial Wire mode (see JTMS description, Pin 35)
Internal pull-up is enabled

TRACEDATA0

O

Synchronous CPU trace data bit 3
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PACFGL[11:8]

34

PC3

I/O Digital

I/O

Either Enable with GPIO_DBGCFG[5],



or enable Serial Wire mode (see JTMS description)

JTDI

I

JTAG data in from debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
Internal pull-up is enabled

TRACECLK

O

Synchronous CPU trace clock
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[15:12]

35

PC4

I/O Digital

I/O

Enable with GPIO_DBGCFG[5]

JTMS

I

JTAG mode select from debugger
Selected when in JTAG mode (default mode)
JTAG mode is enabled after power-up or by forcing nRESET low
Select Serial Wire mode using the ARM-defined protocol through a debug-
ger
Internal pull-up is enabled

SWDIO

I/O

Serial Wire bidirectional data to/from debugger
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol through a debug-
ger
Internal pull-up is enabled

Note:

1.

IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.

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Содержание EM3585

Страница 1: ...1 Rev 1 0 EM3585 EM3585 Zigbee module User s Manual ...

Страница 2: ...3 1 1 Related Documents 3 1 1 1 Ember EM358x Reference Manual 3 1 1 2 ZigBee Specification 3 1 1 3 ZigBee PRO Stack Profile 3 1 1 4 ZigBee Stack Profile 3 1 1 5 EEE 802 15 4 2003 3 1 1 6 EEE 802 11g 3 1 1 7 ARM Cortex M3 Reference Manual 3 1 2 FCC Part15C CNR 247 使用手冊警語 4 ...

Страница 3: ...ZigBee Stack Profile specification Document 064321 is designed to support smaller networks with hundreds of devices in a single network It can be downloaded from the ZigBee website 111 zigbee org ZigBee Alliance membership is required 1 1 5 EEE 802 15 4 2003 This standard defines the protocol and compatible interconnection for data communication devices using low data rate low power and low comple...

Страница 4: ...t This equipment should be installed and operated with minimum distance 20cm between the radiator and your body French Cet appareil radio est conforme au CNR 247 d Industrie Canada L utilisation de ce dispositif est autorisée seulement aux deux conditions suivantes 1 il ne doit pas produire de brouillage et 2 l utilisateur du dispositif doit être prêt à accepter tout brouillage radioélectrique reç...

Страница 5: ...rict timing requirements imposed by the ZigBee and IEEE 802 15 4 2003 standards the EM358x integrates a number of MAC functions AES128 encryption accelerator and automatic CRC handling into the hardware The MAC hardware handles automatic ACK transmission and reception automatic backoff delay and clear channel assessment for transmission as well as automatic filtering of received packets The Ember ...

Страница 6: ..._P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF NC VDD_PADSA PC5 TX_ACTIVE nRESET 48 47 46 45 44 43 42 41 40 39 38 37 1 49 36 2 GND 35 3 34 4 33 5 32 6 EM358x 31 8 29 9 28 10 27 11 26 12 25 PB0 VREF IRQA TRACEDATA2 TIM1CLK TIM2MSK PC4 JTMS SWDIO PC3 JTDI TRACECLK PC2 JTDO SWO TRACEDATA0 SWCLK JTCK PB2 SC1MISO SC1MOSI SC1SCL SC1RXD TIM2C2 PB1 SC1MISO SC1MOSI SC1SDA SC1TXD TIM2C1 PA6 TIM1C3 VDD_PADS P...

Страница 7: ...ernal RX TX switch The EM358x baseband con trols TX_ACTIVE and drives it high VDD_PADS when in TX mode Select alternate output function with GPIO_PCCFGH 7 4 12 nRESET I Active low chip reset internal pull up 13 PC6 I O Digital I O OSC32B I O 32 768 kHz crystal oscillator Select analog function with GPIO_PCCFGH 11 8 nTX_ACTIVE O Inverted TX_ACTIVE signal see PC5 Select alternate output function wit...

Страница 8: ... 6 Enable timer output in TIM2_CCER Select alternate output function with GPIO_PBCFGL 15 12 TIM2C3 see also Pin 22 I Timer 2 channel 3 input Enable remap with TIM2_OR 6 SC1nCTS I UART CTS handshake of Serial Controller 1 Enable with SC1_UARTCFG 5 Select UART with SC1_MODE SC1SCLK O SPI master clock of Serial Controller 1 Either disable timer output in TIM2_CCER or disable remap with TIM2_OR 6 Enab...

Страница 9: ... SC1_SPICFG 4 Select SPI with SC1_MODE 21 PA0 I O Digital I O USBDM where applicable I O USB D signal Select analog function with GPIO_PACFGL 3 0 TIM2C1 see also Pin 30 O Timer 2 channel 1 output Disable remap with TIM2_OR 4 Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL 3 0 TIM2C1 see also Pin 30 I Timer 2 channel 1 input Disable remap with TIM2_OR 4 SC2MOSI O ...

Страница 10: ......

Страница 11: ...troller 2 Either disable timer output in TIM2_CCER or enable remap with TIM2_OR 6 Select TWI with SC2_MODE Select alternate open drain output function with GPIO_PACFGL 7 4 SC2MISO O SPI slave data out of Serial Controller 2 Either disable timer output in TIM2_CCER or enable remap with TIM2_OR 6 Enable slave with SC2_SPICFG 4 Select SPI with SC2_MODE Select alternate output function with GPIO_PACFG...

Страница 12: ...l Controller 2 Either disable timer output in TIM2_CCER or enable remap with TIM2_OR 7 Enable master with SC2_SPICFG 4 Select SPI with SC2_MODE Select alternate output function with GPIO_PACFGL 11 8 SC2SCLK I SPI slave clock of Serial Controller 2 Enable slave with SC2_SPICFG 4 Select SPI with SC2_MODE 25 PA3 I O Digital I O SC2nSSEL I SPI slave select of Serial Controller 2 Enable slave with SC2_...

Страница 13: ...core Enable PTI in Ember software Select alternate output function with GPIO_PACFGH 7 4 nBOOTMODE I Activate FIB monitor instead of main program or bootloader when coming out of reset Signal is active during and immediately after a reset on nRESET Refer to section 7 5 Boot Configuration in Chapter 7 GPIO of the Ember EM358x Reference Manual for details TRACEDATA3 see also Pin 38 O Synchronous CPU ...

Страница 14: ...7 4 SC1SDA I O TWI data of Serial Controller 1 Either disable timer output in TIM2_CCER or disable remap with TIM2_OR 4 Select TWI with SC1_MODE Select alternate open drain output function with GPIO_PBCFGL 7 4 SC1TXD O UART transmit data of Serial Controller 1 Either disable timer output in TIM2_CCER or disable remap with TIM2_OR 4 Select UART with SC1_MODE Select alternate output function with GP...

Страница 15: ...h GPIO_PBCFGL 11 8 SC1RXD I UART receive data of Serial Controller 1 Select UART with SC1_MODE TIM2C2 see also Pin 25 O Timer 2 channel 2 output Enable remap with TIM2_OR 5 Enable timer output in TIM2_CCER Select alternate output function with GPIO_PBCFGL 11 8 TIM2C2 see also Pin 25 I Timer 2 channel 2 input Enable remap with TIM2_OR 5 32 SWCLK I O Serial Wire clock input output with debugger Sele...

Страница 16: ...Either Enable with GPIO_DBGCFG 5 or enable Serial Wire mode see JTMS description JTDI I JTAG data in from debugger Selected when in JTAG mode default mode see JTMS description Pin 35 Internal pull up is enabled TRACECLK O Synchronous CPU trace clock Enable trace interface in ARM core Select alternate output function with GPIO_PCCFGL 15 12 35 PC4 I O Digital I O Enable with GPIO_DBGCFG 5 JTMS I JTA...

Страница 17: ...og function with GPIO_PCCFGL 7 4 TRACEDATA3 see also Pin 27 O Synchronous CPU trace data bit 3 Select 1 2 or 4 wire synchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GPIO_PCCFGL 7 4 39 VDD_MEM Power 1 8 V supply flash RAM 40 PC0 I O High current Digital I O Either enable with GPIO_DBGCFG 5 or enable Serial Wire mode see JTMS descriptio...

Страница 18: ...External interrupt source B TIM1C1 O Timer 1 channel 1 output Enable timer output in TIM1_CCER Select alternate output function with GPIO_PBCFGH 11 8 TIM1C1 I Timer 1 channel 1 input Cannot be remapped 43 PB5 I O Digital I O ADC0 Analog ADC Input 0 Enable analog function with GPIO_PBCFGH 7 4 TIM2CLK I Timer 2 external clock input TIM1MSK I Timer 1 external clock mask input 44 VDD_CORE Power 1 25 V...

Страница 19: ...est and debug purposes If used in this manner the external clock input should be a 1 8 V 50 duty cycle square wave 49 GND Ground Ground supply pad in the bottom center of the package forms Pin 49 See the various Ember EM358x Reference Design documentation for PCB con siderations Note 1 IRQC and IRQD external interrupts can be mapped to any digital I O pin using the GPIO_IRQCSEL and GPIO_IRQDSEL re...

Страница 20: ... 7 mm x 0 90 mm Figure 6 2 illustrates the package drawing 回 B TQP V1EW 令 leeelC 31 U U L U J U _ UP B 1 仁 K 毛主leeelc A 丑一一一一一一十一一一一一一 τ 2J 山鬥門鬥鬥 t J X l一 F JU 叭一的叮沁 3 拈叫迂 E S 況嗨 E吋油O 叫 BC TO 叫叫 F N 1 Id d C 1 扒 r 忙 E 汀 T 凡心 CH λD Figure 6 2 Package Drawing 50 Rev 1 0 三五封建 ...

Страница 21: ...K 5 2 5 3 5 4 L 0 35 0 40 0 45 aaa 0 10 bbb 0 1 ccc 0 08 ddd 0 1 eee 0 1 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 Variation VKKD 4 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components ...

Страница 22: ... EM358x to the footprint the Paste Mask layer should have a 3 x 3 array of circular openings at 1 015 mm diameter spaced approximately 1 625 mm center to center apart as shown in Figure 6 4 This will cause an evenly distributed solder flow and coplanar attachment to the PCB The solder mask layer illustrated in Figure 6 5 should be the same as the copper layer for the EM358x footprint For more info...

Страница 23: ...EM358x Rev 1 0 53 Figure 6 5 Solder Mask Dimensions ...

Страница 24: ...oidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pads 4 A 4x4 array of 1 1 mm square openings on 1 3 mm pitch should be used for the center ground pad Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is p...

Страница 25: ... 55 The final end product must be labeled in a visible area with the following Contains FCC ID NHS EM3585 contains IC 3653A EM3585 The grantee s FCC ID can be used only when all FCC IC compliance requirements are met ...

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