Debug support is described in detail in Chapter 8, and the debug interface is described in the
E31 Core Complex User Guide.
The E31 Core Complex supports 16 high-priority, low-latency local vectored interrupts per-hart.
This Core Complex includes a RISC-V standard platform-level interrupt controller (PLIC), which
supports 127 global interrupts with 7 priority levels. This Core Complex also provides the stan-
dard RISC‑V machine-mode timer and software interrupts via the Core Local Interruptor
(CLINT).
Interrupts are described in Chapter 5. The CLINT is described in Chapter 6. The PLIC is
described in in Chapter 7.
The E31 Core Complex memory system has Tightly Integrated Instruction and Data Memory
sub-systems optimized for high performance. The instruction subsystem consists of a 16 KiB
2-way instruction cache with the ability to reconfigure a single way into a fixed-address tightly
integrated memory. The data subsystem allows for a maximum DTIM size of 64 KiB.
The memory system is described in more detail in Chapter 3.
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