2
Requirements for Use
B4 - 9
CP 443-5 Extended for PROFIBUS / Manual Part B4
Release 6/2005
C79000-G8976-C162-06
S
Whether the CPU supports the functionality for identifying the bus topology in a
DP master system (SFC103) via the CP.
S
DPV1 functionality
S
CiR functionality (DP slave / DP slot, configurable extension)
Notice
ET 200M devices that were assigned to SYNC/FREEZE groups with STEP 7,
must not have modules of the type FM or CP inserted.
Table 2-1
Use with the Current CPU Types
CPU
Order Number of the
CPU
Firmware version
CPU:
6ES7...
Number of AG-SEND or AG-RECV calls at
same time
SYNC/FREEZE functionality
DP-V1 functionality
CiR / HCiR functionality
1)
Activate / deactivate
DP slave
Identify bus
topology
CPU 412
..412 - 1XF04 - 0AB0
As of V4.
24 /24
+
+
+
+
-
As of V4.1
24 /24
+
+
+
+
+
CPU 412-2
..412 - 2XG04 - 0AB0
As of V4.
24 / 24
+
+
+
+
-
As of V4.1
24 / 24
+
+
+
+
+
CPU 414-2
..414 - 2XG04 - 0AB0
As of V4.
24 / 24
+
+
+
+
-
As of V4.1
24 / 24
+
+
+
+
+
CPU 414 - 3
..414 - 3XJ04 - 0AB0
As of V4.
24 / 24
+
+
+
+
-
As of V4.1
24 / 24
+
+
+
+
+
CPU414-4H
..414 - 4HJ04 - 0AB0
As of V4.
24 / 24
-
+
+
-
-
As of
V4.0.5
24 / 24
-
+
+
-
+
CPU 416-2
..416 - 2XK04 - 0AB0
As of V4.
64 / 64
+
+
+
+
-
As of V4.1
64 / 64
+
+
+
+
+
CPU 416 - 3
..416 - 3XL04 - 0AB0
As of V4.
64 / 64
+
+
+
+
-
As of V4.1
64 / 64
+
+
+
+
+
CPU 416F - 2
..416 - 2FK04 - 0AB0
As of V4.
64 / 64
+
+
+
+
-
As of V4.1
64 / 64
+
+
+
+
+
