Shuttle MK32N, Руководство пользователя

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PCI1Master 0 WS Write
When this item enabled, writing to the PCI bus is executed with zero
wait state.
Ø The Choice: Enabled or Disabled.
PCI2 Master 0 WS Write
When this item enabled, writing to the AGP bus is executed with zero
wait state.
Ø The Choice: Enabled or Disabled.
PCI1 Post Write
This Item enabledisable AGP post write function, which means
when cpu accessing the AGP data, the chipset can queue the instruc-
tion when the AGP bus is busy,then write the data when AGP bus is
available .
Ø The Choice: Enabled or Disabled.
PCI2 Post Write
This Item enabledisable PCI post write function, which means when
cpu accessing the PCI data, the chipset can queue the instruction when
the PCI bus is busy, then write the data when AGP bus is available.
Ø The Choice: Enabled or Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
Ø
The Choice: Enabled or Disabled.
Memory Hole
In order to improve performance, some space in memory can be
reserved for ISA cards.
Ø The Choice: Disabled or 15M-16M.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any pro-
gram is written to this memory area, a system error may result.
Ø The choice: Enabled or Disabled.