Shuttle HOT-559, Руководство пользователя

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24 User's Manual
8 Bit I/O Recovery Time
The recovery time is the length of time, measured in CPU clocks, which the system will
delay after the completion of an input/output request. This delay takes place because
the CPU is operating so much after than the input/output bus that the CPU must be
delayed to allow for the completion of the I/O.
This item allows you to determine the recovery time allowed for 8 bit I/O. Choices are
from NA, 1 to 8 CPU clocks.
16-Bit I/O Recovery Time
This item allows you to determine the recovery time allowed for 16 bit I/O. Choices are
from NA, 1 to 4 CPU clocks.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved for ISA
cards. This memory must be mapped into the memory space below 16 MB.
Peer Concurrency
Peer concurrency means that more than one PCI device can be active at a time.
Enabled this item allows multiple PCI devices can be active.
Passive Release
When enabled, the chipset provides a programmable passive release mechanism to
meet the required ISA master latencies.
Delayed Transaction
Since the 2.1 revision of the PCI specification requires much tighter controls on target
and master latency. PCI cycles to or from ISA typically take longer. When enabled, the
chipset provides a programmable delayed completion mechanism to meet the required
target latencies.