Cache Speed Options
This option sets the cache burst read/write cycle. The optimal
setting depends on system clock speed. The settings are2-l-2, 2-
2-2, 3-1-3, or 3-2-3.
·
DRAM Read Wait State
This option sets the memory read wait state. The optimal set
ting depends on system clock speed. The settings are I, 2, or 3
w.s.
DRAM Write Wait State
This option sets the memory write wait state. The optimal set
ting depends on system clock speed. The settings are
0,
I, 2, or
3
w.s.
PCICLK-to-ISA SYSCLK Divsor
This option sets the !SA clock that divide from PC! Clock. The
settings are
PCICLKU2, PCICLKU3,
or
PCICLKU4.
Keyboard Clock Divsor
This option sets the keyboard clock frequency, derive from PCI
Clock. The settings are
PCICLKU2, PCICLKU3, PCICLKU4,
or 7. 16MHz.
L2 Cache mode
This option sets the external cache scheme. The settings are
Write-Through
or
Write-Back.
L 1 Cache mode
This option sets the internal cache scheme of the processor. The
settings are
Write-Through
or
Write-Back.
Main BIOS Cacheable
This feature sets the main BIOS in the FOOO-FFFF area to be
cacheable or non-cacheable. The settings are
Enabled
or
Dis
abled.
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