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CPU to PCI Write Buffer
When this field is Enabled, the writing from CPU to PCI bus is buffered,
to compensate for the speed differences between the CPU and the PCI
bus. When Disabled, the writing is are not buffered and the CPU must
wait until the write is complete before starting another write cycle.
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The Choice: Enabled or Disabled.
PCI Dynamic Bursting
This item allows you to enable/disable the PCI dynamic bursting func-
tion.
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The Choice: Enabled or Disabled.
PCI Master 0 WS Write
When this item enabled, writing to the PCI bus is executed with zero
wait state.
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The Choice: Enabled or Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The Choice: Enabled or Disabled.
PCI #2 Access #1 Retry
When this item disabled, PCI#2 will not be disconnected until access
finishes (default); On the contrary, PCI#2 will be disconnected if max
etries are attempted without success.
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The Choice: Enabled or Disabled.
