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SPEC No.
LD-28204A
MODEL No.
LS013B7DH07
PAGE
18
6-6) Input Signal Timing Chart
6-6-1 Data update mode (1 line)
Updates data of only one specified line. (M0=”Hi”
、
M2
=
”Lo”)
Figure 6-6 Data update mode by 1line
M0: Mode flag. Set for “Hi”. Data update mode (Memory internal data update)
When “Lo”, display mode (maintain memory internal data).
M1: Frame inversion flag.
When “Hi”, outputs VCOM=”Hi”, and when “Lo”, outputs VCOM=”Lo”.
When EXTMODE=”Hi”, it can be “Hi” or “Lo”.
M2: All clear flag.
Refer to 6-6-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “Hi” or “Lo” (“Lo” is recommended.)
※
For gate line address setting, refer to 6-7) Input Signal and Display.
※
M1: Frame inversion flag is enaled when EXTMODE=”Lo”.
※
When SCS becomes
“
Lo
”
, M0 and M2 are cleared.
※
Data write period
Data is being stored in 1
st
latch block of binary driver on panel.
※
Data transfer period
Data written in 1
st
latch is being transferred (written) to pixel internal memory circuit.
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©Copyright 2016 SHARP All rights reserved
©Copyright 2016 SHARP All rights reserved
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