Sharp LC-46X8E/S/RU, Руководство по обслуживанию

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LC-46X8E/S/RU
5 – 9
1.5. IC3501 (RH-iXC163WJQZQ)
1.5.1 Block Diagram
1.5.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
62, 63 CK, CK I The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ's and DM's that are sam-
pled on both edges of the DQS.
22 CKE I Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low indicates the Power down mode or Self refresh mode.
12 CS I CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations con-
tinue.
11 RAS I Latches row addresses on the positive going edge of the CK with RAS low. Enables row access &
precharge.
10 CAS I Latches column addresses on the positive going edge of the CK with CAS low. Enables column
access.
53 WE I Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
1, 28, 7, 34 DQS0-3 I/O Data input and output are synchronized with both edge of DQS.
44, 67, 50, 35 DM0-3 I Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~
DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
40, 78, 41, 42, 2, 46,
3, 4, 26, 65, 27, 66,
29, 68, 30, 69, 48, 5,
49, 6, 51, 8, 9, 52, 31,
32, 71, 33, 37, 38, 75,
39 DQ0-31 I/O Data inputs/Outputs are multiplexed on the same pins.
14, 56 BA0, BA1 I Selects which bank is to be active.