96
LC-26GA5E
LC-32GA5E
LC-32/37GD8E/RU
LC-32/37BT8E/RU
2.6.3. Pin Description (Continued)
Pin list
STi5516
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Table 22: Port 2 PIO signal assignments
Port 2 bit
Input
Output
Bit 0
MAFE_HC1 or NOT_ASC4_RTS
a
Bit 1
MAFE_DOUT or ASC4_TXD
a
Bit 2
MAFE_DIN or ASC4_RXD
a
Bit 3
MAFE_FS or NOT_ASC4_CTS
a
Bit 4
MAFE_SCLK
Bit 5
PWM_CAPTURE0
Bit 6
PWM_COMPARE0
Bit 7
PWM_OUT0
a. Controlled by bit MAFE_OR_UART4_SEL in interconnect register CONFIG_CONTROL_D
(bit 20).
Table 23: Port 3 PIO signal assignments
Port 3 bit
Input
Output
Bit 0
SSC0_MTSR_DIN or SSC0_MRST_DIN
SSC0_MTSR_DOUT or SSC0_MRST_DOUT
a
Bit 1
SSC0_SCLKIN
SSC0_SCLKOUT
Bit 2
SSC1_MTSR_DIN or SSC1_MRST_DIN
SSC1_MTSR_DOUT or SSC1_MRST_DOUT
b
Bit 3
SSC1_SCLK
SSC1_SCLK
Bit 4
NOT_CD_REQ[0] or PCMI_LRCLK
I1284PERILOGICHIGH
Bit 5
Slave mode I1284HOSTLOGICHIGH or
PCMI_DATA
Master mode I1284HOSTLOGICHIGH
Bit 6
NOT_CD_REQ[1] or PCMI_SCLK
I1284INNOTOUT
Bit 7
PWM_OUT1
a. Output function selected by bit 24 in interconnect configuration register
CONFIG_CONTROL_B (COMMS_SSC0_DOUT_MRST_NOTMTSR_MUXSEL)
b. Output function selected by bit 25 in interconnect configuration register
CONFIG_CONTROL_B (COMMS_SSC1_DOUT_MRST_NOTMTSR_MUXSEL)
