Sharp LC-19LE430E, Руководство по обслуживанию

Страница: 71 / 206

2008-03-14
LC-19LE430E/UK, LC-22LE430E/UK, LC-26LE430E/UK, LC-32LE430E/UK
71
· Analog and Digital Multiplexing and Demultiplexing
· A/D and D/A Conversion
· Signal Gating
1.8 U4051 (HY27US08561A-TPCB 256Mb TSOP1-48)
SUMMARY Description
The HYNIX HY27(U/S)S(08/16)561A series is a 32Mx8bit with spare 8Mx16 bit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 2048 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash cells.
A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device)
block.
Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and
margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be
connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27(U/S)S(08/16)561A extended reliability of 100K program/ erase cycles by providing ECC
(Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a
microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly
programmed in another page inside the same array section without the time consuming serial data insertion phase.
This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up, Read ID2 extension.
The Hynix HY27(U/S)S(08/16)561A series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm.
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V : HY27USXX561A
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX561A
Memory Cell Array
= (512+16) Bytes x 32 Pages x 2,048 Blocks
= (256+8) Words x 32 pages x 2,048 Blocks
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes
: HY27(U/S)S08561A
- x16 device: (256 + 8 spare) Words
: HY27(U/S)S16561A
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words