DV-SL8W
55
U20, STEREO D/A CONVERTER (CS4334)
PIN DESCRIPTIONS
No.
Pin Name
I/O
Pin Function and description
1
SDATA
I
Serial Audio Data Input
- two's complement MSB-first serial data is
input on this pin.
The data is clocked into the CS4334/5/8/9 via internal or external
SCLK, and the channel is determined by LRCK.
2
DEM/SCLK
I
De-EmphasIs/External Serial Clock Input
- used for de-emphasis
filter control or external serial clock input.
3
LRCK
I
Left/Right Clock
- determines which channel is currently being input
on the Audio Serial Data Input pin, SDATA.
4
MCLK
I
Master Clock -
frequency must be 256x, 384x, or 512x the input
sample rate in BRM and either 128x or 192x the input sample rate in
HRM.
5
AOUTR
O
Analog Right Channel Output
- typically 3.5 Vp-p for a full-scale input
signal.
6
AGND
I
Analog Ground -
analog ground reference is OV.
7
VA
I
Analog Power
- analog power suuply is nom5V.
8
AOUTL
O
Analog Left Channel Output -
typically 3.5 Vp-p for a full-scale input
signal.
1
2
3
4
SDATA
DEM/SCLK
LRCK
MCLK
SERIAL DATA INPUT
DE-EMPHASIS/SCLK
LEFT/RIGHT CLOCK
MASTER CLOCK
8
7
6
5
AOUTL
VA
AGND
AOUTR
ANALOG LEFT CHANNEL OUTPUT
ANALOG POWER
ANALOG GROUND
ANALOG RIGHT CHANNEL OUTPUT
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