Sharp DV-SL8W, Руководство по обслуживанию

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DV-SL8W
STATE
47
SIGNAL PIN DESCRIPTION
R_A19/GPIO 66 I/O ROM / SRAM/ Flash address bus bit 19 or GPIO
R_OE_B/GPIO 67 I/O ROM / SRAM/ Flash output enable or GPIO
R_WE_B/GPIO 68 I/O ROM / SRAM/ Flash write strobe or GPIO
R_CS1_B/GPIO 69 I/O ROM / SRAM/ Flash chip select #1 (first device) or GPIO
R_CS2_*B/GPIO 70 I/O ROM / SRAM/ Flash chip select #2 or GPIO
R_CS3_B/GPIO 71 I/O ROM / SRAM/ Flash chip select #3 or GPIO
Crystal / Clock Pins (2)
CLKIN 78 I Clock input / crystal in (XTALI)
CLIKOUT 77 O Clock output / crystal out (XTALO)
SDRAM Interface Pins (57)
M_DD[7] 80 I/O SDRAM data bus [7]
M_DD[6] 81 I/O SDRAM data bus [6]
M_DD[5] 82 I/O SDRAM data bus [5]
M_DD[4] 83 I/O SDRAM data bus [4]
M_DD[3] 84 I/O SDRAM data bus [3]
M_DD[2] 86 I/O SDRAM data bus [2]
M_DD[1] 87 I/O SDRAM data bus [1]
M_DD[0] 88 I/O SDRAM data bus [0]
M_WE_B 89 O SDRAM write enable / row precharge
M_CAS_B 91 O SDRAM column address strobe
M_RAS_B 92 O SDRAM row address strobe / precharge
M_CS_B 93 O SDRAM chip select
M_BA0 94 O SDRAM bank select address [0]
M_DD[15] 96 I/O SDRAM data bus [15]
M_DD[14] 97 I/O SDRAM data bus [14]
M_DD[13] 98 I/O SDRAM data bus [13]
M_DD[12] 99 I/O SDRAM data bus [12]
M_DD[11] 101 I/O SDRAM data bus [11]
M_DD[10] 102 I/O SDRAM data bus [10]
M_DD[9] 103 I/O SDRAM data bus [9]
M_DD[8] 104 I/O SDRAM data bus [8]
Priority selection Function
sft_cfg0[0]=1’b1 R_A19 (default)
sft_cfg2[4:2]=3’b010 UART0 TX
(Other) GPIO[32]
Priority selection Function
sft_cfg1[4]=1’b1 R_OE_B (default)
sft_cfg4[2:0]=3’b100 DSP FL0
(Other) GPIO[33]
Priority selection Function
sft_cfg1[5]=1’b1 R_WE_B (default)
sft_cfg4[5:3]=3’b100 DSP FL1
(Other) GPIO[34]
Priority selection Function
sft_cfg1[0]=1’b1 R_CS1_B (default)
(Other) GPIO[13]
Priority selection Function
sft_cfg1[1]=1’b1 R_CS2_B (default)
sft_cfg4[8:6]=3’b100 DSP FL2
(Other) GPIO[35]
Priority selection Function
sft_cfg1[2]=1’b1 R_CS3_B (default)
sft_cfg4[11:9]=3’b100 DSP FLAGOUT
(Other) GPIO[36]