Sharp AQUOS LC-37AD1E, Руководство по обслуживанию

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71
71-1
71-2
LC-37AD1E
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
34,36-44,
D[15:0]
I/O
Data bus D[15:0]
46,48-52 23-26,28,30-32
D[23:16/PTA[7:0]
I/O
Data bus D[23:16]/I/O port A[7:0]
13-18,20,22
D[31:24/PTB[7:0]
I/O
Data bus D[31:24]/I/O port B[7:0]
86,84,82,78-72,
A[25:0]
O
Address bus A[15:0]
70-68-60,56-53 96
CS0
O
Chip select 0
98
CS2/PTK[0]
O/(I/O)
Chip select 2/I/O port K[0]
99
CS3/PTK[1]
O/(I/O)
Chip select 3/I/O port K[1]
100
CS4/PTK[2]
O/(I/O)
Chip select 4/I/O port K[2]
101
CS5/CE1E/PTK[3]
O/(I/O)
Chip select 5/CE1(area 5SPCMIA)/O port K[3]
102
CS6/CE1B
0
Chip select 6/CE1(area 6SPCMIA)
87
BS/PTK[4]
O/(I/O)
Bus cycle startup signal /I/O port K[4]
118
RAS3U/PTE[2]
O/(I/O)
"RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port E[2}"
106
RAS3L/PTJ[0]
O/(I/O)
"RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port J[0}"
119
RAS2U/PTE[1]
O/(I/O)
"RAS(area 2DRAM,SDRAM upper 32MB address)/I/O port E[1}"
107
RAS2L/PTJ[1]
O/(I/O)
"RAS(area 2DRAM,SDRAM upper 32MB address)/I/O portJE[1}"
108
CASLL/CAS/PTJ[2]
O/(I/O)
CAS(DRAM)/CAS(SDRAM)/I/O port J[2] for D7-D0.
110
CASLH/PTJ[3]
O/(I/O)
CAS(DRAM)/I/O port J[3] for D15-D18.
112
CASHL/PTJ[4]
O/(I/O)
CAS(DRAM)/I/O port J[4] for D23-D16.
113
CASHH/PTJ[5]
O/(I/O)
CAS(DRAM)/I/O port J[5] for D31-D24.
116
CAS2L/PTE[6]
O/(I/O)
CAS(area 2DRAM)/I/O port E[6] for D7-D0.
117
CAS2H/PTE[3]
O/(I/O)
CAS(area 2DRAM)/I/O port E[3] for D15-D8.
89
WE0/DQMLL
O
D7-D0 selection signal/DQM(SDRAM)
90
WE1/DQMLU/WE
O
D15-D8 selection signal/DQM(SDRAM)/PCMCIA WE
91
WE2/DQMUL/
O/(I/O)
D23-D16 selection signal/DQM(SDRAM)/PCMCIA I/O port K[6]
ICIORD/PTK[6]
92
WE3/DQMUU/
O/(I/O)
D31-D24 selection signal/DQM(SDRAM)/PCMCIA I/O write/I/O port K[7]
ICIOWR/PTK[7]
93
RD/WR
O
Read/write change signal
88
RD
O
Read strobe
105
CKE/PTK[5]
O/(I/O)
CK enable(Only for SDRAM)/I/O port K[5]
123
WAIT
I
Hardware weight demand.
11-8
IRL[3:0]/IRQ[3:0]/
I
E
xternal interruption demand/I/OportH[3:0]
PTH[3:0]
12
IRQ4/PTH[4]
I
External interruption demand/I/OportH[4]
7
NMI
I
Non maskable interruption demand.
160
IRQOUT
O
Interruption demand output
182
WAKEUP/PTD[3]
O/(I/O)
Interruption demand output at the time of standby mode/I/OportD[3]
159
TCLK/PTH[7]
I/O
Clock input output/I/OportH[7] for TMU/RTC.
191
DREQ0/PTD[4]
I
DMA demand 0/I/OportD[4]
114
DACK0/PTD[5]
O/(I/O)
DMA acknowledge 0/I/O port D[5]
192
DREQ1/PTD[6]
I
DMA demand 0/I/O port D[6]
115
DACK1/PTD[7]
O/(I/O)
DMA acknowledge 1/I/O port D[7]
189
DRAK0/PTD[1]
O/(I/O)
DMA acknowledge 0/I/O port D[1]
190
DRAK1/PTD[0]
O/(I/O)
DMA acknowledge 0/I/O port D[0]
171
RxD0/SCPT[0]
I
Input port [0] for receiving data 0/SCI.
164
TxD0/SCPT[0]
O
Output port [0] for transmission data 0/SCI.
165
SCK0/SCPT[1]
I/O
I/O port [1] for serial clock 0/SCI.
172
RxD1/SCPT[2]
I
Input port [2] for receiving data 1/SCI.
166
TxD1/SCPT[2]
O
Output port [2] for transmission data 1/SCI.
167
SCK1/SCPT[1]
I/O
I/O port [3] for serial clock 1/SCI.
174
RxD2/SCPT[4]
I
Input port [4] for receiving data 2/SCI.
168
TxD2/SCPT[4]
O
Output port [4] for transmission data 2/SCI.
169
SCK2/SCPT[5]
I/O
I/O port [5] for serial clock 2/SCI.
170
RTS2/SCPT[6]
O/(I/O)
Requests to Send 2/for SCI/I/O port [6]
176
CTS2/IRQ5/SCPT[7]
I
Transmitting clearance 2/an external interruption demand/Input port [7] for SCI.
104
CE2B/PTE[5]
O/(I/O)
Chip enable 2/I/O port E[5] for Pc card 0.
126
IOIS16/PTG[7]
I
Write protection/Input port G[7]
103
CE2A/PTE[[4]
O/(I/O)
Chip enable 2/I/O port E[4] for PC card 1.
146,149
CAP[1:2]
—
External capacity terminal for PLL [1:2]
156
EXTAL
I
External clock/Crystal oscillation element terminal
155
XTAL
O
Crystal oscillation element terminal
162
CKIO
I/O
System clock input and output
5
EXTAL2
I
C
rystal oscillation element terminal for RTC.
4
XTAL
O
C
rystal oscillation element terminal for RTC.
193
RESETP
I
Power-on reset demand
124
RESETM
I
Manual reset demand
Pin No
.
Pin Name
I/O
Pin Function
122
BREQ
I
Bus demand
121
BACK
O
Bus acknowledge.
2,1,144
MD[2:0]
I
Clock mode setup
196,195
MD[4:3]
I
Area 0 bus wide setup.
197
MD5
I
Endian setup
194
CA
O
Chip active.
158,157
STATUS[1:0]/
I/O
Processor status[1:0]/I/O port J[7:6]
PTJ[7:6]
204-199
AN[5:0]/PTL[6:7]
I
A
/D conversion input[5:0]/input port L[5:0]
206,207
AN[6:7]/DA[1:0]/
I/O
A/D conversion input[6:7]/D/A conversion output[1:0]/input port L[6:7]
PTL[6:7]
177-180,185-188
PTC[7:0]/PINT[7:0]
I/O
I/O port C[7:0]/port Interruption [7:0]
184
PTD[2]/RESETOUT
I/O
I/O port D[2]/reset output
120,94
PTE[0]/PTE[7]
I/O
I/O port E[0]/I/O port E[7]
136-143
PTF[7:0]/PINT[15:8]
I
I/O port F[7:0]/port Interruption [15:8]
127-131,135
PTG[6:0]
I
I/O port G[6:0]
125
PTH[5]/ADTRG
I
I/O port H[5]/Analog trigger
151
PTH[6]
I
I/O port H[6]
21,29,35,47,59,
Vcc
—
power supply (3.3V)
71,81,85,97,111, 134,154,163,175, 183 145,150
Vcc(PLL)
—
power supply (3.3V)
3
Vcc(RTC)
—
power supply (3.3V)
205
Avcc
—
Analog power supply (3.3V)
19,27,33,45,57,
Vss
—
power supply (0V)
69,79,83,95,109, 132,152,153,161, 173,181 147,148
Vss(PLL)
—
power supply (0V)
6
Vss(TRC)
—
power supply (0V)
198,208
Avss
—
Analog power supply (0V)