LC
-
32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S
7 – 7
2.3. IC3501/3502 (RH-iXC790WJQZQ)
2.3.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
J8,K8
CK, CK#
I
Clock:
CK and CK# are differential clock inputs. All address and control input signals are sampled on the cross-
ing of the positive edge of CK and negative edge of CK#.
Output (read) data is referenced to the crossings of CK and CK# (both directions of crossing).
K2
CKE
I
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-
put drivers.
Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all bank idle), or Active
Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for
self refresh exit.
After VREF has become stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to
this input.
CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK#,
ODT and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during self
refresh.
L8
CS#
I
Chip Select:
All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.
K9
ODT
I
On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM.
When enabled, ODT is only applied to each DQ, DQS, DQS#, RDQS, RDQS#, and DM signal for x4/x8
configuration.
For x16 configuration, ODT is applied to each DQ, UDQS/UDQS#. LDQS/LDQS#, UDM and LDM signal.
The ODT pin will be ignored if the Extended Mode Register Set (EMRS) is programmed to disable ODT.
K7,L7,K3
RAS#, CAS#, WE#
I
Command Inputs:
RAS#, CAS# and WE# (along with CS#) define the command being entered.
F3,B3
DM
(VDM) (UDM)
I
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident
with that input data during a Write access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For x8 device, the function of DM or RDQS /RDQS# is enabled by EMRS command.
L2,L3,L1
BA0, BA1, BA2
I
Bank Address Inputs:
BA0,BA1and BA2 define to which bank an Active, Read, Write or Precharge command is being applied.
Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
M8,M3,M
7,N2,N8,
N3,N7,P2
,P8,P3,M
2,P7,R2
A0 - A13
I
Address Inputs: Provide the row address for Active commands, and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective
bank.
A10 is sampled during a pre charge command to determine whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be Precharge, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
G8,G2,H
7,H3,H1,
H9,F1,F9,
C8,C2,D7
,D3,D1,D
9,B1,B9
DQ0 - DQ15
I/O
Data Input/Output: Bi-directional data bus.
B7,A8,
F7,E8
(DQS), (DQS#)
(LDQS0),(DQS0#)
or
(DQS3),(DQS3#)
(DQS2),(DQS2#)
I/O
A2,E2,R3
,R7,R8
NC
-
No Connect: No internal electrical connection is present.
A1,E1,J9,
M9,R1
VDD
-
Power Supply: +1.8V
±
0.1V.
A9,C1,C3
,C7,C9,E
9,G1,G3,
G7,G9
VDDQ
-
DQ Power Supply: +1.8V
±
0.1V.
A3,E3,J3,
N1,P9
VSS
-
Ground.
