LC
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32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S
7 – 25
2.18. IC1504 (VHi-1Q)
2.18.1 Block Diagram
2.18.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
HDMI RX Port Pins
68
R0X0P
I
TMDS input port 0 data pairs.
67
R0X0N
I
70
R0X1P
I
69
R0X1N
I
72
R0X2P
I
71
R0X2N
I
66
R0XCP
I
TMDS input port 0 clock pair.
65
R0XCN
I
4
R1X0P
I
TMDS input port 1 data pairs.
3
R1X0N
I
6
R1X1P
I
5
R1X1N
I
8
R1X2P
I
7
R1X2N
I
2
R1XCP
I
TMDS input port 1 clock pair
1
R1XCN
I
14
R2X0P
I
TMDS input port 2 data pairs.
13
R2X0N
I
16
R2X1P
I
15
R2X1N
I
TMDS
T
X
CEC_A
37
CEC
Controller
CEC_D
60,61
58,59
56,57
DSDA1,
DSCL1
TMDS
DPLL/DEC
SCDT
HDCP REG
HDMI PORT PROCESSOR
43,
44
LOCAL
I2C
29
30
14,13
16,15
18,17
68,67
70,69
72,71
38
POWER_DOWN
HPD0
HPD1
PORT2
BOOTING
SEQUENCER
51
DSDA4,
DSCL4
CPI REG
62,63
39,
40
33,
34
HDCP ENGINE
22,21,
24,23,
26,25
PORT1
CSCL
CSDA
2,1
R0PWR5V
R1PWR5V
R2PWR5V
R3PWR5V
R4PWR5V
ALWAYS_ON
31
35
41
45
SiI9287
NV RAM
CONFIG
STATUS REG
INT
DSDA2,
DSCL2
48,
47
SBVCC
PORT0
HDMI DATAPATH
4,3
6,5
8,7
20,13
50
VCC33
52
TMDS
E
NC
32
36
42
46
49
OTP
9,27,64
EDID SRAM
DSDA3,
DSCL3
PORT3
R0X0P/N
R0X1P/N
R0X2P/N
R0XCP/N
12,11
54
53
66,65
MICOM_VCC33
DDC0
DDC1
DDC2
DDC3
DDC4
MHL Control
MHL
DP
DSDA0,
DSCL0
R1X0P/N
R1X1P/N
R1X2P/N
R1XCP/N
R2X0P/N
R2X1P/N
R2X2P/N
R2XCP/N
R3X0P/N
R3X1P/N
R3X2P/N
R3XCP/N
HPD2
HPD3
TX0P/N
TX1P/N
TX2P/N
TXCP/N