2. Circuit descriptions
A. Maiin PWB (MCU)
(1) CPU signal table
CPU pin table
Model without SPF
PIN No
Signal code
Input/output
Operating
1
/CS1
Output
Chip Select for SRAM
2
/CS0
Output
Chip Select for EPROM
3
D-GND
4
D-GND
5
5V
6
A0
Output
Address Bus (NC-pull up)
7
A1
Output
Address Bus
8
A2
Output
Address Bus
9
A3
Output
Address Bus
10
Output
D-GND
11
A4
Output
Address Bus
12
A5
Output
Address Bus
13
A6
Output
Address Bus
14
A7
Output
Address Bus
15
A8
Output
Address Bus
16
A9
Output
Address Bus
17
A10
Output
Address Bus
18
A11
Output
Address Bus
19
Output
D-GND
20
A12
Output
Address Bus
21
A13
Output
Address Bus
22
A14
Output
Address Bus
23
A15
Output
Address Bus
24
A16
Output
Address Bus
25
A17
Output
Address Bus (for 2Mbit EPROM) - (NC)
26
A18
Output
Address Bus (NC-pull up)
27
A19
Output
Address Bus (NC-pull up)
28
D-GND
29
A20
Output
Address Bus (NC-pull up)
30
NC-pull up
31
NC-pull up
32
(Interruption input)
NC-pull up
33
(MHPS)
Interruption level input
Mirror Home Position Sensor
34
/CPUSYNC
Interruption level input
Horizontal Synchronous (from G/A)
35
D-GND
36
D-GND
37
ZC
Interruption level input
Zero-cross signal
38
/ASICINT
Interruption level input
Intterupt from G/A
39
5V
40
D0
Data input/output
Data Bus
41
D1
Data input/output
Data Bus
42
D2
Data input/output
Data Bus
43
D3
Data input/output
Data Bus
44
D-GND
AL-1000/1010
12-3
