52
network, eight inductors in the series arm, and five more capacitors in shunt
on the output arm, all arranged in binary increments. Relays are provided in
conjunction with each lumped constant and allow removal or entry as desired.
A network having 64 values on input shunt C, 32 values of output shunt C, and
up to 256 values of series L is possible with the manipulation of these 38 relays.
8
8..4
4
IIM
MP
PE
ED
DA
AN
NC
CE
E D
DE
ET
TE
EC
CT
TO
OR
R
RF transformers T3 and T2 drive the impedance bridge which is balanced at 50
ohms. T2 samples the line current and thus D2 outputs a negative DC level pro-
portional to line current. A tertiary winding on transformer T3 provides a line
voltage sample to D7 which provides a positive voltage proportional to line
voltage. R34 and R26 act as a summing network for the current and voltage
signals, with ratios chosen such that, at 50 ohms, the summed signals result in
a balanced or zero voltage condition.
If the line impedance goes to high, the signal from the voltage sensor will be
rela-tively higher than the current sensor, which will result in a net positive
output voltage from the summing network.
Similarly, a low line impedance will result in more output from the current
sensor, resulting in a net negative output voltage from the summing network.
The summing network output is shifted to a 0 to 5V range, then fed to the
processor's A to D converter ports, and used within the microcontroller.
8
8..5
5 V
VS
SW
WR
R D
DE
ET
TE
EC
CT
TO
OR
R
A directional coupler comprises a current transformer T1 and a voltage trans-
former T3, in conjunction with termination resistors R22 and R19. The coupler
is inserted in the 50-ohm transmission line between the input connector, J5,
and the tuning network. The forward power is measured across termination
R22 and reflected power is measured across termination R19. Diode D1 gener-
ates a positive DC voltage proportional to forward power and D8 generates a
positive DC voltage proportional to reflected power. The forward DC output is
fed to a voltage divider consisting of R35 and R23. These voltages are input to
the RF power detector and to an A to D converter port of the processor. The
reflected DC output passes through a voltage divider consisting of R39 and R40,
and then it also goes to an A to D converter port of the processor.
8
8..6
6 P
PH
HA
AS
SE
E D
DE
ET
TE
EC
CT
TO
OR
R
A phase detector is formed by T2, A1, and their associated components. This
detector indicates the state of any reactance associated with the antenna cou-
SGC Inc. SGC Building, 13737 S.E. 26th St. Bellevue, WA 98005 USA
P.O. Box 3526, 98009 Fax: 425-746-6384 Tel: 425- 746-6310 or 1-800-259 7331
E-mail: [email protected] Web site: http://www.sgcworld.com
© 1998 SGC Inc
SG-235 Manual