52
set by the voltage divider, the comparator output will go high, indicating a
VSWR higher than 4:1 or 2:1, and will light display indicators, DS3 and DS4.
Note that the full output from the FORWARD power detector is connected
through transistor inverter Q4 to IC-3C, a CMOS gate connected as an inverter.
It is permissible to eliminate a comparator on the FORWARD sensor line since
this signal is typically much larger in amplitude than the output signals from
the summing network. Forward power is indicated by DS6.
7
7..1
12
2 P
PH
HA
AS
SE
E D
DE
ET
TE
EC
CT
TO
OR
R
A phase detector is formed by T1, A1 and their associated components. This
detector indicates the state of any reactance associated with the antenna cou-
pler as noted from the generator. A line current sample is compared in phase
with a voltage sample in a double balanced mixer. Output polarity is positive
for a net capacitive reactance. The output of the phase detector A1, is con -
nected to comparator IC-15B, which goes high when the line reactance is
inductive and is indicated by DS5.
7
7..1
13
3 T
TH
HE
E C
CO
ON
NT
TR
RO
OL
L D
DE
EV
VIIC
CE
E
((C
CP
PU
U -- C
CE
EN
NT
TR
RA
AL
L P
PR
RO
OC
CE
ES
SS
SIIN
NG
G U
UN
NIIT
T))
A tune-up algorithm, which is contained in the memory of the computer sys-
tem, actually implements the antenna matching. The computer is designed
around the CMOS MC146805E2 CPU which features a versatile instruction set
and on-chip timer and RAM. The antenna coupler relays are controlled
through 1C9, a MM5480 decoder/driver. The MM5480 is used as a serial to par-
allel interface port, and the clock and data inputs of the MM5480 are driven
from CPU ports PA1 and PA0, respectively. During operation, data is trans-
ferred into the CPU under program control from the array of sensor/compara-
tors. Basically, the program monitors the status of the input sensors and start-
ing from a preset condition baseline, manipulates the RF elements through its
control algorithm which results in a correctly tuned condition. When the
tuning algorithm is complete, the computer creates a table in non-volatile
memory which correlates the status of the various network relays with the
applied RF frequency. This table is stored in EPROM 1C8 and is the basis of the
exclusive learning feature of the SG-230. After it has stored and latched the
network status, the CPU returns to the "STOP" mode and waits for another
"TUNE REQUEST" condition. When a "TUNE REQUEST" is received, the first step
in the control algorithm is to measure the frequency of the signal which has
generated the request. From the frequency data, the computer then searches
the table stored in 1C8 for any frequency/network status which may be stored.
SGC Inc. SGC Building, 13737 S.E. 26th St. Bellevue, WA 98005 USA
P.O. Box 3526, 98009 Fax: 425-746-6384 Tel: 425- 746-6310 or 1-800-259 7331
E-mail: [email protected] Web site: http://www.sgcworld.com
© 1998 SGC Inc
SG-230 Manual