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SensL © 2011
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USER MANUAL
HRM-TDC
SensL © 2011
20
> Sensl Integrated Environment (sie) > Using The Sensl Integrated Environment (sie)
Updating the FPGA should only be carried out if you are instructed to do so by SensL. This procedure requires a
valid RPD file as provided by SensL.
Failure to carry out this process correctly may render the module inoperable resulting in the need to return it to SensL
for reconfiguration.
Figure 10 SIE Module Information screen
“HISTOGRAM –TCSPC” (Histogram Single-stop)
When this page is launched the top half will display a graph page. Left click on this graph to reveal the configuration
settings. The size of the configuration and graph area can be adjusted by dragging the partition to suite. Figure 11
show this page with the partition adjusted to reveal the entire configuration controls.
Programmable Clock Output
The Programmable Clock Output is made available for all modes and is used to set the frequency and duty cycle of
the internal programmable clock. This clock is available at an SMA output for test purposes. This clock is provided
for testing and diagnostics. The clock will exhibit a level of jitter that would not be suitable for accurate measurements
as part of an experiment.
External Clock Period
This should be set to the period of the external LASER clock.