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CHAPTER 6
Adaptive clocking
A technique in which J-Link / J-Trace sends out a clock signal and waits for the returned
clock from the target device before generating the next clock pulse. The technique allows
the J-Link / J-Trace interface unit to adapt to different signal drive capabilities, different
cable lengths and variable target clock speeds. Adaptive clocking can be used when it is
supported by the connected target device.
RESET
Abbreviation of System Reset. The electronic signal which causes the target system other
than the TAP controller to be reset. This signal is also known as “nSRST” “nSYSRST”, “nRST”,
or “nRESET” in some other manuals. See also nTRST.
nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller
to be reset. This signal is known as nICERST in some other manuals. See also nSRST.
RTCK
Returned TCK. The signal which allows Adaptive Clocking.
TCK
The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO.
TDI
The electronic signal input to a TAP controller from the data source (upstream). Usually,
the TDI signal of J-Link is connected to the TDI of the first TAP controller in a JTAG chain.
TDO
The electronic signal output from a TAP controller to the data sink (downstream). Usually,
the TDO signal of J-Link is connected to the TDO of the last TAP controller in a JTAG chain.
TMS
The electronic signal Test Mode Select is an input to the TAP controller and it is used to
select different stages of state machine. It is clocked in into the TAP controller using the
TCK signal.(upstream). Usually, the TMS output signal of J-Link is connected to the TMS
input of the first TAP controller in a JTAG chain. For Cortex-M CPUs this signal may also
be used as the bidirectional data signal SWDIO when the CPU is accessed in serial wire
debug mode SWD.
SWD
A serial communication protocol for Cortex M CPUs which may used for communication with
a debug device as an alternative communication channel to JTAG. The SWD communication
uses less pins.
SWDIO
The bidirectional electronic signal for communication of a Cortex M CPU accessed in serial
wire debug mode. Normally, the TMS input pin of the Cortex M CPU is used as SWDIO pin
in serial wire mode.
SWCLK
The electronic signal which times data on the SWDIO data line used in serial wire debug
mode. The SWCLK pin is typically the TCK pin used as JTAG clock input, when JTAG is also
supported by the device.
J-Link-OB-STM32F072-128KB-Cortex-M User Guide
(UM08029)
© 2004-2017 SEGGER Microcontroller GmbH
