SBC-C57
SBC-C57 User Manual - Rev. First Edition: 1.0 - Author: S.O. - Reviewed by R.Z. - Copyright © 2021 SECO S.p.A.
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3.3.4
LVDS connector
SBC-C57 can be interfaced to LCD displays using its LVDS interface on CN18,
which allows connecting 18 or 24 bit, single or dual channel displays. This interface
is implemented using a DSI to LVDS bridge (TI SN65DSI84), which allow the
implementation of a Dual Channel LVDS, with a maximum supported resolution of
1920x1200 @ 60Hx (dual channel mode). Such an interface is derived from the
combination of the processor
’
s MIPI-DSI #0 (LVDS channel A) and MIPI-DSI #1 (LVDS
channel B) Interfaces.
When eDP interface is present (by factory configuration) and connected, this interface
can only be used in single channel mode on LVDS channel B.
For the connection, a connector type HR A1014WA-S-2x25P or equivalent (2 x 25p, male, straight, P1, low
profile, polarised) is provided.
Mating connector: HR A1014H-2X25P with HR A1014-T female crimp terminals.
Alternative mating connector, MOLEX 501189-5010 with crimp terminals series 501334.
On the same connectors, are also implemented signals for direct driving of display
’
s backlight: voltages
(VCC_LCD and VCC_BLT) and control signals (LCD Panel enable signal LVDS_PPEN, Backlight enable signal
BLT_EN, digital and analog Backlight Brightness Control signal, respectively BLT_CTRL and LVDS_BLT_ANA).
Output values of VCC_LCD and VCC_BLT can be configured using jumpers as indicated in par. 3.3.5.
There are also signals necessary for driving I2C touchscreens (I2C signals, reset and interrupt request signals).
When building a cable for connection of LVDS displays, please take care of twist as tight as possible differential
pairs
’
signal wires, in order to reduce EMI interferences. Shielded cables are also recommended.
Here following the signals related to LVDS management:
/ LVDS_A0-: LVDS Channel #0 differential data pair #0.
/ LVDS_A1-: LVDS Channel #0 differential data pair #1.
/ LVDS_A2-: LVDS Channel #0 differential data pair #2.
/ LVDS_A3-: LVDS Channel #0 differential data pair #3.
LVD / LVDS_A_CLK-: LVDS Channel #0 differential Clock.
/ LVDS_B0-: LVDS Channel #1 differential data pair #0.
LVDS connector CN18
Pin
Signal
Pin
Signal
1
VCC_LCD
2
VCC_BLT
3
VCC_LCD
4
VCC_BLT
5
VCC_LCD
6
VCC_BLT
7
+3V3_RUN
8
GND
9
GND
10
11
12
LVDS_A0-
13
LVDS_A1-
14
GND
15
GND
16
17
18
LVDS_A2-
19
LVDS_A3-
20
GND
21
GND
22
LVD
23
24
LVDS_A_CLK-
25
LVDS_B0-
26
GND
27
GND
28
29
30
LVDS_B1-
31
LVDS_B2-
32
GND
33
GND
34
35
LVD
36
LVDS_B3-
37
LVDS_B_CLK-
38
GND
39
GND
40
GND
41
BLT_EN
42
BLT_CTRL
43
LVDS_BLT_ANA
44
LVDS_PPEN
45
TOUCH_SCL
46
TOUCH_RST
47
TOUCH_SDA
48
TOUCH_INT#
49
TOUCH_SDA
50
TOUCH_SCL
