Digital CCD Line Scan Camera SK 10680 DJR ( Rev.1.4. / 20.09.2005 ) - Manual
Page
5
7. Timing Diagram
*
The rising edge of ‘SOS’ should not occur within a range of 5 to 30 ns before leading edge of ‘MCLK’.
**
CLT = Camera Line Transfer ( internal line scan camera Signal)
***
The signal ‘LVAL’ contains a ‘CLT’ pulse at the line beginning, which is required for the synchronisation of
the Schäfter+Kirchhoff Interface boards.
If requested, the CCD line scan camera is available without ‘CLT’ pulse at the line beginning of the ‘LVAL’.
Order Code: SK 10680 DJR-3
The pixels determining the black level value are the 3th to the 51th before pixel no. 1.
i = Isolation pixels
o = Overclocking
MCLK
SOS *
CLT**
CCLK
LVAL***
Data
Video
internally
Input
Output
ca. 50 ns
97 Clock Cycles
N= 10680 Clock Cycles
6 Clock Cycles min.
20 ns
0
0
10678 10679 10680
10680
