Digital CCD Line Scan Camera SK 10680 DJR ( Rev.1.4. / 20.09.2005 ) - Manual
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3. Connecting and Control Signals
P1
P2
J1
Camera backside
J1 = Centronics 36pin-male, P1 = Offset adj., P2 = Gain adj.
Pin Assignment
Voltage Supply
+ 5 V ± 5% ca. 180 mA
+15 V ± 5% ca. 50 mA
-12V to -15 V ± 5% ca. 15 mA
4. Digital Control SIgnals
Input Control Signals:
The Low Voltage Differential input Signals (LVDS) are converted into TTL conform signals inside of the CCD camera.
The camera uses only the control signals "Clock" (MCLK) and "Start Of Scan" (SOS) for operation. The camera
electronic responds to the rising signal edges that should be ‘sharp’ and free from noise.
The frequency of the "Start of Scan" signal determines the total count of line scans per second. On the rising edge
of this signal all the accumulated charges inside the pixels will be tranferred to the analog shift register of the sensor.
The shift register (transport register) will be read out with the ‘Clock’ signal.
The ‘Clock’ signal frequency gives the read-out rate for single pixel informations of the linear sensor. This is just the
rate of the video output signal of the camera. Every rising edge of ‘Clock’ transfers the next following pixel’s char-
ges to the video output amplifier. Delay time at this point is about 50 ns.
The ‘Clock’ and the ‘SOS’ signals need not to be syncronized. The ‘Clock’ frequency should be set to a sufficient
large number to ensure enough ‘Clock’ pulses to read out the line sensor completely between two successive
‘SOS’ signals. The SK 10680 DJR Camera needs 10784 ‘Clock’ signals to read out a line scan completely. Gene-
rally, transferring a larger number of ‘Clock’ pulses as needed is unproblematic.
MCLK: Master-Clock in: determines the pixel transport frequency, maximum 5 MHz. Low voltage differential input.
SOS:
Start of Scan: 50 ns minimum pulslength. Differential input.
The frequency of the ‘SOS’ signal determines the line frequency readout of the camera.
The charges of the sensor are accumulated while the ‘SOS’ signal is low. This way the length of the ‘low’
period can be used to effectively control the actual integration time at a fixed or rapidly changing line
frequency.
The rising edge of the ‘SOS’ signal initiates the readout operation and the charges are transferred into the
onchip analog shift register.
Output Signals:
‘Clock’ and ‘Start of Scan’ signals are echoed at the camera output to monitor system timings. These
signals, like the input ‘Clock’ and ‘Start of Scan’ signals, are ‘Low Voltage Differential signals’ (LVDS).
CCLK: Camera-Clock out / Low Voltage Differential driver.
LVAL: Line Valid / Differential driver. A ‘High’-level shows the availability of valid pixel data at the AD-converter out-
put. The signal ‘LVAL’ contains a ‘CLT’ pulse at the beginning of the line, necessary to synchronise
Schäfter+Kirchhoff
- Interface boards.
D0-D7: 8 bit digital video output (8 x Low Voltage Differential driver LVDS) D0=LSB, D7=MSB
Miniature Centronics 36 pin Connector (male)
Signal
Pin
Pin
Signal
GND
18
O O
36
GND
(+5V) VCC
17
O O
35
VCC
(+5V)
GND
16
O O
34
D7
- out
(+5V)
VCC
15
O O
33
D7
+ out
CCLK - out
14
O O
32
D6
- out
CCLK + out
13
O O
31
D6
+ out
LVAL - out
12
O O
30
D5
- out
LVAL + out
11
O O
29
D5
+ out
SOS - in
10
O O
28
D4
- out
SOS + in
9
O O
27
D4
+ out
MCLK - in
8
O O
26
D3
- out
MCLK + in
7
O O
25
D3
+ out
GND
6
O O
24
D2
- out
(-12V bis -15V)
VEE
5
O O
23
D2
+ out
(+15V)
VDD
4
O O
22
D1
- out
(+15V)
VDD
3
O O
21
D1
+ out
GND
2
O O
20
DO
- out
Analog Video A out
1
O O
19
DO
+ out
(for test only)
