17
IntReq1* Interrupt Vector. The vector will normally be read inside the Interrupt Service
Routine. The vector does not have to be read if the IndustryPack does nothing more with
an IACK cycle than output the vector. Although this is the case with most IndustryPacks,
please verify for each IndustryPack by referring to its documentation. Some
IndustryPacks require the vector to be read to clear the interrupt.
Write Posting
The PLX PCI 9080 chip always posts writes to its internal write FIFO regardless of how
the PCI 2.1 compliant bit in the Mode/Arbitration Register is set. This keeps the PCI bus
access at a minimum, usually taking five PCI clocks, but can cause problems on the PCI-
60A if the software is not aware of this feature. A problem can occur when a write is
made to an IndustryPack that does not respond or is not present. The PCI bus
transaction will complete normally. However, the local bus side of the PCI 9080 will get
hung up waiting for the IndustryPack to respond. The next access to the PCI-60A will
then put the PCI bus in an infinite retry loop when the PCI 9080 issues a retry for the new
access while it waits for the previous access to complete. The easiest way around this
problem is to use the Auto Acknowledge feature, which will automatically complete the
local bus cycle if the IndustryPack does not respond within 3.2 µsecs. See the
IndustryPack Bus Time-Out
and
Status and Control Register Bit Map
sections of this
manual.
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