S.B.C. Elettronica S.p.A. - Engineering Division
HPDxxN – High Power User’s Manual
46
A/D
Pr 3
Pr 2
F/D
Pr 5
Pr 6
Pr 4
left-sw
right-sw
stop
offset
main ref.
S/H
Pr 1
+
-
full scale
ref. 1
full scale
ref. 2
max fq ref.
internal reference
reserved reference
Pr 7
b40.0
b40.2
b40.3
Pr 8
Pr 9
Pr 10
Pr 11
ramps values
Pr 12
ramp
value
b40.4
b40.5
b40.6
motor speed
Pr 14
Pr 15
Pr 13
Pr 0
+
-
b40.7
forward
zero speed
at speed
over speed
b 41.0
b 41.1
b 41.2
b 41.3
high
low
over
Pr 16
Pr 17
Pr 18
speed control
+
-
Pr 19
user current limit
thermal image limit
Pr 33
reserved current limit
Pr 21
aux reference
Pr 22
max
torque
demand
b40.8
band-width
limitator
over voltage
under voltage
over current
resolver break
motor over temp.
power stage over temp
Pr 23
b41.12
present
trip code
last
b41.4
drive ok
b41.5
hardware
enable
b40.9
software
enable
HIGH PERFORMANCE DRIVE
MAIN BLOCK DIAGRAM
Pr 25
SOFTWARE RELEASE
Pr 26
BAUD RATE
Pr 27
SERIAL LINK ADDRESS
Pr 28
SHAFT POSITION
Pr 29
MOTOR POLES
Pr 30
RES. PHASE SHIFT
DESCRIPTION
Param.
R/W
N
Y
Y
N
Y
Y
external trip
aux. trip
Pr 31
OPERATING MODE
Y
Pr 32
RATED SPEED
Y
output short circuit
B41.6
PRE ALARM
N
Pr 35
torque demand
Pr 36
I2T ACCUMOLATOR
N
Pr 37
BRAKE RESISTOR USE
N
b 41.7
b 41.8
b40.11
analog out
Pr 38
Vout aux
B40.1
VIBRATION STOP.
Y
b40.13
b40.12
Pr 24
drive enabled
rated current
b41.11
Pr 20
DC BUS VOLTAGE
N
Pr 39
PHASE ADVANCE
Y
B42.0
B42.1
B42.2
ENCODER OUT RESOL.
Y
B42.5
QUADRATURE / FD
Y
B41.14
B41.15
EXTERNAL OPM
FLAGS
N
B40.10
LOW VOLTAGE OP.
Y
Pr 34
GAIN FOR TACHO
PLC check-sum
PAR. check-sum